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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Terminal
signal
Signal name
re_rs_usr_wreg_0
Write data 6
06_clk100m_reg
re_rs_usr_wreg_0
Write data 7
07_clk100m_reg
re_rs_usr_wreg_0
Write data 8
08_clk100m_reg
re_rs_usr_wreg_0
Write data 9
09_clk100m_reg
re_rs_usr_wreg_0
Write data 10
0a_clk100m_reg
re_rs_usr_wreg_0
Write data 11
0b_clk100m_reg
re_rs_usr_wreg_0
Write data 12
0c_clk100m_reg
re_rs_usr_wreg_0
Write data 13
0d_clk100m_reg
re_rs_usr_wreg_0
Write data 14
0e_clk100m_reg
re_rs_usr_wreg_0
Write data 15
0f_clk100m_reg
re_rs_usr_wreg_0
Write data 16
10_clk100m_reg
re_rs_usr_wreg_0
Write data 17
11_clk100m_reg
re_rs_usr_wreg_0
Write data 18
12_clk100m_reg
re_rs_usr_wreg_0
Write data 19
13_clk100m_reg
re_rs_usr_wreg_0
Write data 20
14_clk100m_reg
re_rs_usr_wreg_0
Write data 21
15_clk100m_reg
re_rs_usr_wreg_0
Write data 22
16_clk100m_reg
re_rs_usr_wreg_0
Write data 23
17_clk100m_reg
re_rs_usr_wreg_0
Write data 24
18_clk100m_reg
re_rs_usr_wreg_0
Write data 25
19_clk100m_reg
re_rs_usr_wreg_0
Write data 26
1a_clk100m_reg
re_rs_usr_wreg_0
Write data 27
1b_clk100m_reg
re_rs_usr_wreg_0
Write data 28
1c_clk100m_reg
re_rs_usr_wreg_0
Write data 29
1d_clk100m_reg
re_rs_usr_wreg_0
Write data 30
1e_clk100m_reg
re_rs_usr_wreg_0
Write data 31
1f_clk100m_reg
re_rs_usr_wreg_0
Write data 32
20_clk100m_reg
re_rs_usr_wreg_0
Write data 33
21_clk100m_reg
re_rs_usr_wreg_0
Write data 34
22_clk100m_reg
Bit
Input/
Polarity
Initial
width
output
value
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
16
Input
0000H
Appendix 5 List of User Circuit Block Terminals
1shot
Sync clock
Feq
Clock
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
APPX
613
A
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Troubleshooting
