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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
616
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_wreg_0
Write data 93
5d_clk100m_reg
re_rs_usr_wreg_0
Write data 94
5e_clk100m_reg
re_rs_usr_wreg_0
Write data 95
5f_clk100m_reg
re_rs_usr_wreg_0
Write data 96
60_clk100m_reg
re_rs_usr_wreg_0
Write data 97
61_clk100m_reg
re_rs_usr_wreg_0
Write data 98
62_clk100m_reg
re_rs_usr_wreg_0
Write data 99
63_clk100m_reg
re_rs_usr_wreg_0
Write data 100
64_clk100m_reg
re_rs_usr_wreg_0
Write data 101
65_clk100m_reg
re_rs_usr_wreg_0
Write data 102
66_clk100m_reg
re_rs_usr_wreg_0
Write data 103
67_clk100m_reg
re_rs_usr_wreg_0
Write data 104
68_clk100m_reg
re_rs_usr_wreg_0
Write data 105
69_clk100m_reg
re_rs_usr_wreg_0
Write data 106
6a_clk100m_reg
re_rs_usr_wreg_0
Write data 107
6b_clk100m_reg
re_rs_usr_wreg_0
Write data 108
6c_clk100m_reg
re_rs_usr_wreg_0
Write data 109
6d_clk100m_reg
re_rs_usr_wreg_0
Write data 110
6e_clk100m_reg
re_rs_usr_wreg_0
Write data 111
6f_clk100m_reg
re_rs_usr_wreg_0
Write data 112
70_clk100m_reg
re_rs_usr_wreg_0
Write data 113
71_clk100m_reg
re_rs_usr_wreg_0
Write data 114
72_clk100m_reg
re_rs_usr_wreg_0
Write data 115
73_clk100m_reg
re_rs_usr_wreg_0
Write data 116
74_clk100m_reg
re_rs_usr_wreg_0
Write data 117
75_clk100m_reg
re_rs_usr_wreg_0
Write data 118
76_clk100m_reg
re_rs_usr_wreg_0
Write data 119
77_clk100m_reg
re_rs_usr_wreg_0
Write data 120
78_clk100m_reg
re_rs_usr_wreg_0
Write data 121
79_clk100m_reg
Bit
Input/
Polarity
width
output
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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