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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
618
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_wreg_0
Write data 151
97_clk100m_reg
re_rs_usr_wreg_0
Write data 152
98_clk100m_reg
re_rs_usr_wreg_0
Write data 153
99_clk100m_reg
re_rs_usr_wreg_0
Write data 154
9a_clk100m_reg
re_rs_usr_wreg_0
Write data 155
9b_clk100m_reg
re_rs_usr_wreg_0
Write data 156
9c_clk100m_reg
re_rs_usr_wreg_0
Write data 157
9d_clk100m_reg
re_rs_usr_wreg_0
Write data 158
9e_clk100m_reg
re_rs_usr_wreg_0
Write data 159
9f_clk100m_reg
re_rs_usr_wreg_0
Write data 160
a0_clk100m_reg
re_rs_usr_wreg_0
Write data 161
a1_clk100m_reg
re_rs_usr_wreg_0
Write data 162
a2_clk100m_reg
re_rs_usr_wreg_0
Write data 163
a3_clk100m_reg
re_rs_usr_wreg_0
Write data 164
a4_clk100m_reg
re_rs_usr_wreg_0
Write data 165
a5_clk100m_reg
re_rs_usr_wreg_0
Write data 166
a6_clk100m_reg
re_rs_usr_wreg_0
Write data 167
a7_clk100m_reg
re_rs_usr_wreg_0
Write data 168
a8_clk100m_reg
re_rs_usr_wreg_0
Write data 169
a9_clk100m_reg
re_rs_usr_wreg_0
Write data 170
aa_clk100m_reg
re_rs_usr_wreg_0
Write data 171
ab_clk100m_reg
re_rs_usr_wreg_0
Write data 172
ac_clk100m_reg
re_rs_usr_wreg_0
Write data 173
ad_clk100m_reg
re_rs_usr_wreg_0
Write data 174
ae_clk100m_reg
re_rs_usr_wreg_0
Write data 175
af_clk100m_reg
re_rs_usr_wreg_0
Write data 176
b0_clk100m_reg
re_rs_usr_wreg_0
Write data 177
b1_clk100m_reg
re_rs_usr_wreg_0
Write data 178
b2_clk100m_reg
re_rs_usr_wreg_0
Write data 179
b3_clk100m_reg
Bit
Input/
Polarity
width
output
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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