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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
622
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_wreg_1
Write data 267
0b_clk100m_reg
re_rs_usr_wreg_1
Write data 268
0c_clk100m_reg
re_rs_usr_wreg_1
Write data 269
0d_clk100m_reg
re_rs_usr_wreg_1
Write data 270
0e_clk100m_reg
re_rs_usr_wreg_1
Write data 271
0f_clk100m_reg
re_rs_usr_wreg_11
Write data 272
0_clk100m_reg
re_rs_usr_wreg_11
Write data 273
1_clk100m_reg
re_rs_usr_wreg_11
Write data 274
2_clk100m_reg
re_rs_usr_wreg_11
Write data 275
3_clk100m_reg
re_rs_usr_wreg_11
Write data 276
4_clk100m_reg
re_rs_usr_wreg_11
Write data 277
5_clk100m_reg
re_rs_usr_wreg_11
Write data 278
6_clk100m_reg
re_rs_usr_wreg_11
Write data 279
7_clk100m_reg
re_rs_usr_wreg_11
Write data 280
8_clk100m_reg
re_rs_usr_wreg_11
Write data 281
9_clk100m_reg
re_rs_usr_wreg_11
Write data 282
a_clk100m_reg
re_rs_usr_wreg_11
Write data 283
b_clk100m_reg
re_rs_usr_wreg_11
Write data 284
c_clk100m_reg
re_rs_usr_wreg_11
Write data 285
d_clk100m_reg
re_rs_usr_wreg_11
Write data 286
e_clk100m_reg
re_rs_usr_wreg_11
Write data 287
f_clk100m_reg
re_rs_usr_wreg_1
Write data 288
20_clk100m_reg
re_rs_usr_wreg_1
Write data 289
21_clk100m_reg
re_rs_usr_wreg_1
Write data 290
22_clk100m_reg
re_rs_usr_wreg_1
Write data 291
23_clk100m_reg
re_rs_usr_wreg_1
Write data 292
24_clk100m_reg
re_rs_usr_wreg_1
Write data 293
25_clk100m_reg
re_rs_usr_wreg_1
Write data 294
26_clk100m_reg
re_rs_usr_wreg_1
Write data 295
27_clk100m_reg
Bit
Input/
Polarity
width
output
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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