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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
626
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_wreg_1
Write data 383
7f_clk100m_reg
re_rs_usr_wreg_1
Write data 384
80_clk100m_reg
re_rs_usr_wreg_1
Write data 385
81_clk100m_reg
re_rs_usr_wreg_1
Write data 386
82_clk100m_reg
re_rs_usr_wreg_1
Write data 387
83_clk100m_reg
re_rs_usr_wreg_1
Write data 388
84_clk100m_reg
re_rs_usr_wreg_1
Write data 389
85_clk100m_reg
re_rs_usr_wreg_1
Write data 390
86_clk100m_reg
re_rs_usr_wreg_1
Write data 391
87_clk100m_reg
re_rs_usr_wreg_1
Write data 392
88_clk100m_reg
re_rs_usr_wreg_1
Write data 393
89_clk100m_reg
re_rs_usr_wreg_1
Write data 394
8a_clk100m_reg
re_rs_usr_wreg_1
Write data 395
8b_clk100m_reg
re_rs_usr_wreg_1
Write data 396
8c_clk100m_reg
re_rs_usr_wreg_1
Write data 397
8d_clk100m_reg
re_rs_usr_wreg_1
Write data 398
8e_clk100m_reg
re_rs_usr_wreg_1
Write data 399
8f_clk100m_reg
re_rs_usr_wreg_1
Write data 400
90_clk100m_reg
re_rs_usr_wreg_1
Write data 401
91_clk100m_reg
re_rs_usr_wreg_1
Write data 402
92_clk100m_reg
re_rs_usr_wreg_1
Write data 403
93_clk100m_reg
re_rs_usr_wreg_1
Write data 404
94_clk100m_reg
re_rs_usr_wreg_1
Write data 405
95_clk100m_reg
re_rs_usr_wreg_1
Write data 406
96_clk100m_reg
re_rs_usr_wreg_1
Write data 407
97_clk100m_reg
re_rs_usr_wreg_1
Write data 408
98_clk100m_reg
re_rs_usr_wreg_1
Write data 409
99_clk100m_reg
re_rs_usr_wreg_1
Write data 410
9a_clk100m_reg
re_rs_usr_wreg_1
Write data 411
9b_clk100m_reg
Bit
Input/
Polarity
width
output
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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