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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Digital output
u_do2_top_b0
control part
Digital output
u_do2_top_b1
control part
Digital output
u_do2_top_b2
control part
Digital output
u_do2_top_e0
control part
Digital output
u_do2_top_e1
control part
Digital output
u_do2_top_e2
control part
Digital I/O
u_dio2_top_b0
control part
Digital I/O
u_dio2_top_b0
control part
Digital I/O
u_dio2_top_b1
control part
Digital I/O
u_dio2_top_b1
control part
Digital I/O
u_dio2_top_b2
control part
Digital I/O
u_dio2_top_b2
control part
APPX
630
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_wreg_1f
Write data 499
3_clk100m_reg
re_rs_usr_wreg_1f
Write data 500
4_clk100m_reg
re_rs_usr_wreg_1f
Write data 501
5_clk100m_reg
re_rs_usr_wreg_1f
Write data 502
6_clk100m_reg
re_rs_usr_wreg_1f
Write data 503
7_clk100m_reg
re_rs_usr_wreg_1f
Write data 504
8_clk100m_reg
re_rs_usr_wreg_1f
Write data 505
9_clk100m_reg
re_rs_usr_wreg_1f
Write data 506
a_clk100m_reg
re_rs_usr_wreg_1f
Write data 507
b_clk100m_reg
re_rs_usr_wreg_1f
Write data 508
c_clk100m_reg
re_rs_usr_wreg_1f
Write data 509
d_clk100m_reg
re_rs_usr_wreg_1f
Write data 510
e_clk100m_reg
re_rs_usr_wreg_1f
Write data 511
f_clk100m_reg
re_rs_usr_logmod
User circuit logging
e_sel_1_0_clk100
mode selection
m_reg
re_rs_usr_micon_s
MCU system error
yserr_clk100m_reg
notification
uc_iob0_y_clk100
Digital output
m_reg
signal (B0)
uc_iob1_y_clk100
Digital output
m_reg
signal (B1)
uc_iob2_y_clk100
Digital output
m_reg
signal (B2)
uc_ioe0_y_clk100
Digital output
m_reg
signal (E0)
uc_ioe1_y_clk100
Digital output
m_reg
signal (E1)
uc_ioe2_y_clk100
Digital output
m_reg
signal (E2)
uc_iob0_dio485_o
Digital output
_clk100m_reg
signal (digital I/O
B0)
uc_iob0_dio485_e
Digital I/O control
n_clk100m_reg
(B0)
uc_iob1_dio485_o
Digital output
_clk100m_reg
signal (digital I/O
B1)
uc_iob1_dio485_e
Digital I/O control
n_clk100m_reg
(B1)
uc_iob2_dio485_o
Digital output
_clk100m_reg
signal (digital I/O
B2)
uc_iob2_dio485_e
Digital I/O control
n_clk100m_reg
(B2)
Bit
Input/
Polarity
width
output
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
16
Input
1
Input
1
Input
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
1
Output
1
Output
1
Output
1
Output
1
Output
1
Output
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0H
100MHz
0H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0H
100MHz
0H
100MHz
0H
100MHz
0H
100MHz
0H
100MHz
0H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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