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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
632
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
uc_rs_usr_alrreg_
Always read
05_clk100m_reg
register 5
uc_rs_usr_alrreg_
Always read
06_clk100m_reg
register 6
uc_rs_usr_alrreg_
Always read
07_clk100m_reg
register 7
uc_rs_usr_alrreg_
Always read
08_clk100m_reg
register 8
uc_rs_usr_alrreg_
Always read
09_clk100m_reg
register 9
uc_rs_usr_alrreg_
Always read
0a_clk100m_reg
register 10
uc_rs_usr_alrreg_
Always read
0b_clk100m_reg
register 11
uc_rs_usr_alrreg_
Always read
0c_clk100m_reg
register 12
uc_rs_usr_alrreg_
Always read
0d_clk100m_reg
register 13
uc_rs_usr_alrreg_
Always read
0e_clk100m_reg
register 14
uc_rs_usr_alrreg_
Always read
0f_clk100m_reg
register 15
re_rs_usr_rreg_00
Read data 0
0_clk100m_reg
re_rs_usr_rreg_00
Read data 1
1_clk100m_reg
re_rs_usr_rreg_00
Read data 2
2_clk100m_reg
re_rs_usr_rreg_00
Read data 3
3_clk100m_reg
re_rs_usr_rreg_00
Read data 4
4_clk100m_reg
re_rs_usr_rreg_00
Read data 5
5_clk100m_reg
re_rs_usr_rreg_00
Read data 6
6_clk100m_reg
re_rs_usr_rreg_00
Read data 7
7_clk100m_reg
re_rs_usr_rreg_00
Read data 8
8_clk100m_reg
re_rs_usr_rreg_00
Read data 9
9_clk100m_reg
re_rs_usr_rreg_00
Read data 10
a_clk100m_reg
re_rs_usr_rreg_00
Read data 11
b_clk100m_reg
re_rs_usr_rreg_00
Read data 12
c_clk100m_reg
re_rs_usr_rreg_00
Read data 13
d_clk100m_reg
re_rs_usr_rreg_00
Read data 14
e_clk100m_reg
re_rs_usr_rreg_00f
Read data 15
_clk100m_reg
re_rs_usr_rreg_01
Read data 16
0_clk100m_reg
re_rs_usr_rreg_01
Read data 17
1_clk100m_reg
Bit
Input/
Polarity
width
output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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Troubleshooting
