Table of Contents
Advertisement
Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Terminal
signal
Signal name
re_rs_usr_rreg_0fa
Read data 250
_clk100m_reg
re_rs_usr_rreg_0fb
Read data 251
_clk100m_reg
re_rs_usr_rreg_0fc
Read data 252
_clk100m_reg
re_rs_usr_rreg_0fd
Read data 253
_clk100m_reg
re_rs_usr_rreg_0fe
Read data 254
_clk100m_reg
re_rs_usr_rreg_0ff
Read data 255
_clk100m_reg
re_rs_usr_rreg_10
Read data 256
0_clk100m_reg
re_rs_usr_rreg_10
Read data 257
1_clk100m_reg
re_rs_usr_rreg_10
Read data 258
2_clk100m_reg
re_rs_usr_rreg_10
Read data 259
3_clk100m_reg
re_rs_usr_rreg_10
Read data 260
4_clk100m_reg
re_rs_usr_rreg_10
Read data 261
5_clk100m_reg
re_rs_usr_rreg_10
Read data 262
6_clk100m_reg
re_rs_usr_rreg_10
Read data 263
7_clk100m_reg
re_rs_usr_rreg_10
Read data 264
8_clk100m_reg
re_rs_usr_rreg_10
Read data 265
9_clk100m_reg
re_rs_usr_rreg_10
Read data 266
a_clk100m_reg
re_rs_usr_rreg_10
Read data 267
b_clk100m_reg
re_rs_usr_rreg_10
Read data 268
c_clk100m_reg
re_rs_usr_rreg_10
Read data 269
d_clk100m_reg
re_rs_usr_rreg_10
Read data 270
e_clk100m_reg
re_rs_usr_rreg_10f
Read data 271
_clk100m_reg
re_rs_usr_rreg_11
Read data 272
0_clk100m_reg
re_rs_usr_rreg_11
Read data 273
1_clk100m_reg
re_rs_usr_rreg_11
Read data 274
2_clk100m_reg
re_rs_usr_rreg_11
Read data 275
3_clk100m_reg
re_rs_usr_rreg_11
Read data 276
4_clk100m_reg
re_rs_usr_rreg_11
Read data 277
5_clk100m_reg
re_rs_usr_rreg_11
Read data 278
6_clk100m_reg
Bit
Input/
Polarity
Initial
width
output
value
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
Appendix 5 List of User Circuit Block Terminals
1shot
Sync clock
Feq
Clock
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
APPX
641
A
Advertisement
Table of Contents
Troubleshooting
