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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
642
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_rreg_11
Read data 279
7_clk100m_reg
re_rs_usr_rreg_11
Read data 280
8_clk100m_reg
re_rs_usr_rreg_11
Read data 281
9_clk100m_reg
re_rs_usr_rreg_11
Read data 282
a_clk100m_reg
re_rs_usr_rreg_11
Read data 283
b_clk100m_reg
re_rs_usr_rreg_11
Read data 284
c_clk100m_reg
re_rs_usr_rreg_11
Read data 285
d_clk100m_reg
re_rs_usr_rreg_11
Read data 286
e_clk100m_reg
re_rs_usr_rreg_11f
Read data 287
_clk100m_reg
re_rs_usr_rreg_12
Read data 288
0_clk100m_reg
re_rs_usr_rreg_12
Read data 289
1_clk100m_reg
re_rs_usr_rreg_12
Read data 290
2_clk100m_reg
re_rs_usr_rreg_12
Read data 291
3_clk100m_reg
re_rs_usr_rreg_12
Read data 292
4_clk100m_reg
re_rs_usr_rreg_12
Read data 293
5_clk100m_reg
re_rs_usr_rreg_12
Read data 294
6_clk100m_reg
re_rs_usr_rreg_12
Read data 295
7_clk100m_reg
re_rs_usr_rreg_12
Read data 296
8_clk100m_reg
re_rs_usr_rreg_12
Read data 297
9_clk100m_reg
re_rs_usr_rreg_12
Read data 298
a_clk100m_reg
re_rs_usr_rreg_12
Read data 299
b_clk100m_reg
re_rs_usr_rreg_12
Read data 300
c_clk100m_reg
re_rs_usr_rreg_12
Read data 301
d_clk100m_reg
re_rs_usr_rreg_12
Read data 302
e_clk100m_reg
re_rs_usr_rreg_12f
Read data 303
_clk100m_reg
re_rs_usr_rreg_13
Read data 304
0_clk100m_reg
re_rs_usr_rreg_13
Read data 305
1_clk100m_reg
re_rs_usr_rreg_13
Read data 306
2_clk100m_reg
re_rs_usr_rreg_13
Read data 307
3_clk100m_reg
Bit
Input/
Polarity
width
output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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Troubleshooting
