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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
APPX
648
Appendix 5 List of User Circuit Block Terminals
Terminal
signal
Signal name
re_rs_usr_rreg_1c
Read data 453
5_clk100m_reg
re_rs_usr_rreg_1c
Read data 454
6_clk100m_reg
re_rs_usr_rreg_1c
Read data 455
7_clk100m_reg
re_rs_usr_rreg_1c
Read data 456
8_clk100m_reg
re_rs_usr_rreg_1c
Read data 457
9_clk100m_reg
re_rs_usr_rreg_1c
Read data 458
a_clk100m_reg
re_rs_usr_rreg_1c
Read data 459
b_clk100m_reg
re_rs_usr_rreg_1c
Read data 460
c_clk100m_reg
re_rs_usr_rreg_1c
Read data 461
d_clk100m_reg
re_rs_usr_rreg_1c
Read data 462
e_clk100m_reg
re_rs_usr_rreg_1cf
Read data 463
_clk100m_reg
re_rs_usr_rreg_1d
Read data 464
0_clk100m_reg
re_rs_usr_rreg_1d
Read data 465
1_clk100m_reg
re_rs_usr_rreg_1d
Read data 466
2_clk100m_reg
re_rs_usr_rreg_1d
Read data 467
3_clk100m_reg
re_rs_usr_rreg_1d
Read data 468
4_clk100m_reg
re_rs_usr_rreg_1d
Read data 469
5_clk100m_reg
re_rs_usr_rreg_1d
Read data 470
6_clk100m_reg
re_rs_usr_rreg_1d
Read data 471
7_clk100m_reg
re_rs_usr_rreg_1d
Read data 472
8_clk100m_reg
re_rs_usr_rreg_1d
Read data 473
9_clk100m_reg
re_rs_usr_rreg_1d
Read data 474
a_clk100m_reg
re_rs_usr_rreg_1d
Read data 475
b_clk100m_reg
re_rs_usr_rreg_1d
Read data 476
c_clk100m_reg
re_rs_usr_rreg_1d
Read data 477
d_clk100m_reg
re_rs_usr_rreg_1d
Read data 478
e_clk100m_reg
re_rs_usr_rreg_1df
Read data 479
_clk100m_reg
re_rs_usr_rreg_1e
Read data 480
0_clk100m_reg
re_rs_usr_rreg_1e
Read data 481
1_clk100m_reg
Bit
Input/
Polarity
width
output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
16
Output
Initial
1shot
Sync clock
value
Feq
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
0000H
100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
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