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Connection destination
Block name
Instance
name
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Terminal
signal
Signal name
re_rs_usr_rreg_1e
Read data 482
2_clk100m_reg
re_rs_usr_rreg_1e
Read data 483
3_clk100m_reg
re_rs_usr_rreg_1e
Read data 484
4_clk100m_reg
re_rs_usr_rreg_1e
Read data 485
5_clk100m_reg
re_rs_usr_rreg_1e
Read data 486
6_clk100m_reg
re_rs_usr_rreg_1e
Read data 487
7_clk100m_reg
re_rs_usr_rreg_1e
Read data 488
8_clk100m_reg
re_rs_usr_rreg_1e
Read data 489
9_clk100m_reg
re_rs_usr_rreg_1e
Read data 490
a_clk100m_reg
re_rs_usr_rreg_1e
Read data 491
b_clk100m_reg
re_rs_usr_rreg_1e
Read data 492
c_clk100m_reg
re_rs_usr_rreg_1e
Read data 493
d_clk100m_reg
re_rs_usr_rreg_1e
Read data 494
e_clk100m_reg
re_rs_usr_rreg_1ef
Read data 495
_clk100m_reg
re_rs_usr_rreg_1f0
Read data 496
_clk100m_reg
re_rs_usr_rreg_1f1
Read data 497
_clk100m_reg
re_rs_usr_rreg_1f2
Read data 498
_clk100m_reg
re_rs_usr_rreg_1f3
Read data 499
_clk100m_reg
re_rs_usr_rreg_1f4
Read data 500
_clk100m_reg
re_rs_usr_rreg_1f5
Read data 501
_clk100m_reg
re_rs_usr_rreg_1f6
Read data 502
_clk100m_reg
re_rs_usr_rreg_1f7
Read data 503
_clk100m_reg
re_rs_usr_rreg_1f8
Read data 504
_clk100m_reg
re_rs_usr_rreg_1f9
Read data 505
_clk100m_reg
re_rs_usr_rreg_1fa
Read data 506
_clk100m_reg
re_rs_usr_rreg_1fb
Read data 507
_clk100m_reg
re_rs_usr_rreg_1fc
Read data 508
_clk100m_reg
re_rs_usr_rreg_1fd
Read data 509
_clk100m_reg
re_rs_usr_rreg_1fe
Read data 510
_clk100m_reg
Bit
Input/
Polarity
Initial
width
output
value
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
Appendix 5 List of User Circuit Block Terminals
1shot
Sync clock
Feq
Clock
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
APPX
649
A
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Troubleshooting
