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Provided pattern warning list
No. Target file
1
Common to all provided
patterns
2
Common to all provided
patterns
3
Common to all provided
patterns
4
FNA_TOP_01010101.log
5
FNA_TOP_01010102.log
6
FNA_TOP_01010103.log
7
FNA_TOP_01010104.log
8
FNA_TOP_01010105.log
9
FNA_TOP_01010106.log
10
FNA_TOP_01010107.log
11
FNA_TOP_01010108.log
*1 In , a different numerical value is entered for each pattern. The ignored assignments for the sample circuit are shown below.
No. Name
1
Fast Output Enable
Register
2
Fast Output Enable
Register
3
Fast Output Enable
Register
4
Fast Output Enable
Register
5
Fast Output Enable
Register
6
Fast Output Enable
Register
7
Fast Output Enable
Register
8
Fast Output Enable
Register
9
Global Signal
10
Global Signal
11
Global Signal
12
Global Signal
13
Global Signal
14
Global Signal
15
Global Signal
APPX
712
Appendix 13 Warning List
Corresponding part
# Warning: DONT_CARE value for read_during_write_mode_port_a is not supported in Stratix
device family, it might cause incorrect behavioural simulation result
# Warning:
# Warning:
### Warning ### Need to wait []us and keep CKE=0 at least 10 ns prior to releasing reset
### Warning ### Need to wait []us after reset releasing and prior to CKE=1.
Ignored Entity
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
altdq_dqs2_acv_connect_to_hard_
phy_cyclonev
top1
top1
top1
top1
top1
top1
top1
Ignored
Ignored To
From
output_path_gen[0].oe_reg
output_path_gen[1].oe_reg
output_path_gen[2].oe_reg
output_path_gen[3].oe_reg
output_path_gen[4].oe_reg
output_path_gen[5].oe_reg
output_path_gen[6].oe_reg
output_path_gen[7].oe_reg
u_pt2_top|dc3_top|p0|umemphy|uio_pads|
dq_ddio[0].read_capture_clk_buffer
u_pt2_top|dc3_top|p0|umemphy|uio_pads|
dq_ddio[1].read_capture_clk_buffer
u_pt2_top|dc3_top|p0|umemphy|uread_dat
apath|reset_n_fifo_wraddress[0]
u_pt2_top|dc3_top|p0|umemphy|uread_dat
apath|reset_n_fifo_wraddress[1]
u_pt2_top|dc3_top|p0|umemphy|uread_dat
apath|reset_n_fifo_write_side[0]
u_pt2_top|dc3_top|p0|umemphy|uread_dat
apath|reset_n_fifo_write_side[1]
u_pt2_top|dc3_top|p0|umemphy|ureset|ph
y_reset_mem_stable_n
Description
It states that Stratix
devices are not
supported. Since this
FPGA is the cyclone
device, there is no
problem.
Pseudo warning output
from the DDR3L
SDRAM simulation
model. There is no
problem.
*1
Pseudo warning output
*1
from the DDR3L
SDRAM simulation
model. There is no
problem.
Ignored
Ignored
Value
Source
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
ON
Compiler or HDL
Assignment
OFF
QSF Assignment
OFF
QSF Assignment
OFF
QSF Assignment
OFF
QSF Assignment
OFF
QSF Assignment
OFF
QSF Assignment
OFF
QSF Assignment
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