Page 1 DatasheetDirect.com Your dedicated source for free downloadable datasheets. Over one million datasheets Optimized search function Rapid quote option Free unlimited downloads Visit www.datasheetdirect.com to get your free datasheets. This datasheet has been downloaded by http://www.datasheetdirect.com/...
Page 2: Table Of Contents
DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX...
Page 3 DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX...
Page 4 Rev. 0 DSP56309 24-Bit Digital Signal Processor UserÕs Manual Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598...
Page 5 Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended.
Page 6: Dsp56309 Overview
MANUAL CONVENTIONS ......1-5 DSP56309 FEATURES ......1-6 DSP56309 CORE DESCRIPTION .
Page 7 MEMORY MAPS ....... . . 3-9 INTERNAL I/O MEMORY MAP ..... . 3-18 DSP56309UM/D MOTOROLA...
Page 8 Port D Signals and Registers..... . . 5-4 5.2.4 Port E Signals and Registers..... . . 5-4 MOTOROLA DSP56309UM/D...
Page 9 HPCR Host Enable (HEN) Bit 6 ....6-14 6.5.6.8 HPCR Reserved Bit 7......6-14 DSP56309UM/D MOTOROLA...
Page 10 Interrupt Vector Register (IVR) ....6-28 6.6.5 Receive Byte Registers (RXH: RXM: RXL) ... 6-28 6.6.6 Transmit Byte Registers (TXH:TXM:TXL) ... . 6-29 MOTOROLA DSP56309UM/D...
Page 11 CRB Serial Output Flag 1 (OF1) Bit 1 ..7-16 7.4.2.2 CRB Serial Control Direction 0 (SCD0) Bit 2 ..7-16 7.4.2.3 CRB Serial Control Direction 1 (SCD1) Bit 3 ..7-16 viii DSP56309UM/D MOTOROLA...
Page 12 ESSI Time Slot Register (TSR) ....7-34 7.4.9 Transmit Slot Mask Registers (TSMA, TSMB) ..7-34 7.4.10 Receive Slot Mask Registers (RSMA, RSMB)..7-35 MOTOROLA DSP56309UM/D...
Page 13 SCR Transmitter Enable (TE) Bit 9 ....8-10 8.3.1.9 SCR Idle Line Interrupt Enable (ILIE) Bit 10..8-11 DSP56309UM/D MOTOROLA...
Page 14 Port E Direction Register (PRRE) ....8-27 8.5.3 Port E Data Register (PDRE) ..... 8-28 MOTOROLA DSP56309UM/D...
Page 15 Timer Pulse (Mode 1) ......9-18 9.4.1.3 Timer Toggle (Mode 2) ......9-19 DSP56309UM/D MOTOROLA...
Page 16 Core Status (OS0, OS1) Bits 6-7 ....10-9 10.4.3.8 Reserved Bits 8-23 ......10-9 MOTOROLA DSP56309UM/D xiii...
Page 17 Trace Buffer ....... . . 10-21 10.10 SERIAL PROTOCOL DESCRIPTION ....10-22 10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS ..10-23 DSP56309UM/D MOTOROLA...
Page 18 DSP56300 RESTRICTIONS ..... . . 11-12 11.5 DSP56309 BOUNDARY SCAN REGISTER ... 11-13 MOTOROLA...
Page 19 INTERRUPT EQUATES ......B-15 APPENDIX C DSP56309 BSDL LISTING ....C-1 APPENDIX D PROGRAMMING REFERENCE .
Page 20 LIST OF FIGURES Figure 1-1 DSP56309 Block Diagram......1-14 Figure 2-1 Signals Identified by Functional Group ....2-4 Figure 3-1 Default Settings (0, 0, 0) .
Page 21 ESSI Receive Slot Mask Register B (RSMB)....7-10 Figure 7-9 ESSI Clock Generator Functional Block Diagram ... 7-12 xviii DSP56309UM/D MOTOROLA...
Page 22 Port E Data Register (PDRE) ......8-29 Figure 9-1 Triple Timer Module Block Diagram ..... . 9-4 MOTOROLA DSP56309UM/D...
Page 23 Status Register (SR) ....... . . D-15 Figure D-2 Operating Mode Register (OMR) ......D-16 DSP56309UM/D MOTOROLA...
Page 24 Port C Registers (PCRC, PRRC, PDRC) ....D-37 Figure D-24 Port D Registers (PCRD, PRRD, PDRD) ....D-38 MOTOROLA DSP56309UM/D...
Page 25 Figure D-25 Port E Registers (PCRE, PRRE, PDRE) ....D-39 xxii DSP56309UM/D MOTOROLA...
Page 26 On Chip Memory ........1-12 Table 2-1 DSP56309 Functional Signal Groupings ....2-3 Table 2-2 Power Inputs .
Page 27 Memory Locations for Data RAM ......3-9 Table 4-1 DSP56309 Operating Modes ......4-4 Table 4-2 Interrupt Sources .
Page 28 Breakpoint 0 Condition Select Table ....10-13 Table 10-9 Breakpoint 1 Read/Write Select Table ....10-13 MOTOROLA DSP56309UM/D...
Page 29 JTAG Instructions ........11-8 Table 11-2 DSP56309 BSR Bit Definitions ......11-13 Table D-1 Internal I/O Memory Map .
Page 30: Section 1 Dsp56309 Overview
SECTION 1 DSP56309 OVERVIEW MOTOROLA DSP56309UM/D...
Page 31 MANUAL CONVENTIONS ......1-5 DSP56309 FEATURES ......1-6 DSP56309 CORE DESCRIPTION .
Page 32: Introduction
You can obtain these documents, as well as MotorolaÕs DSP development tools, through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information about this DSP, access the Motorola DSP home page at the address on the back cover of this document.
Page 33 Ð The On-Chip Emulation (OnCEª) module, which is accessed through the JTAG port Section 11ÑJTAG Port Ð Specifics of the Joint Test Action Group (JTAG) port on the DSP56309 Appendix AÑBootstrap Programs Ð Bootstrap code used for the DSP56309 Appendix BÑEquates Ð...
Page 34: Manual Conventions
DSP56309 Overview Manual Conventions MANUAL CONVENTIONS This manual uses the following conventions: ¥ Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). ¥ Bits within a register are indicated AA[n:m], n>m, when more than one bit is involved in a description.
Page 35: Dsp56309 Features
Ð the reset function, written as reset. DSP56309 FEATURES The DSP56309 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56309 uses the DSP56300 core, a high-performance engine with a single clock cycle per instruction. The DSP56300 core provides up to twice the performance of Motorola's popular DSP56000 core family, while retaining code compatibility.
Page 36: Dsp56309 Core Description
A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. The DSP56309 targets telecommunications applications, such as multi-line voice/data/fax processing, video conferencing, audio applications, control, and general digital signal processing.
Page 37: Dsp56300 Core Functional Blocks
¥ PCU ¥ PLL and Clock Oscillator ¥ JTAG TAP and OnCE module ¥ Memory In addition, the DSP56309 provides a set of on-chip peripherals, described in Section 1.10. 1.6.1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.
Page 38: Multiplier-Accumulator (Mac)
DSP56309 Overview DSP56300 Core Functional Blocks All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following operation without penalty.
Page 39: Program Control Unit (Pcu)
DSP56309 Overview DSP56300 Core Functional Blocks specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU. 1.6.3 Program Control Unit (PCU) The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception processing.
Page 40: Pll And Clock Oscillator
DSP56309 Overview DSP56300 Core Functional Blocks ¥ SPÑstack pointer ¥ OMRÑoperating mode register ¥ SCÑstack counter register The PCU also includes a hardware system stack (SS). 1.6.4 PLL and Clock Oscillator The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, and skew elimination;...
Page 41: On-Chip Memory
DSP56309 Overview DSP56300 Core Functional Blocks The OnCE module provides a means of interacting with the DSP56300 core and its peripherals non-intrusively so that a user can examine registers, memory, or on-chip peripherals. This facilitates hardware and software development on the DSP56300 core processor.
Page 42: Internal Buses
¥ Y memory address bus (YAB) for carrying Y memory addresses throughout the core All internal buses on the DSP56300 family members are 16-bit buses except the PDB, which is a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56309. MOTOROLA DSP56309UM/D...
Page 43: Dsp56309 Block Diagram
Address Two 56-bit Accumulators Controller Controller Generator OnCEª 56-bit Barrel Shifter MODD/IRQA MODC/IRQB RESET MODB/IRQC PINIT/NMI MODA/IRQD AA0456 Figure 1-1 DSP56309 Block Diagram Note: See Section 1.6.6 On-Chip Memory on page 1-12 for details on memory size. 1-14 DSP56309UM/D MOTOROLA...
Page 44: Direct Memory Access (Dma)
¥ Triggering from interrupt lines, all peripherals, and DMA channels 1.10 DSP56309 ARCHITECTURE OVERVIEW The DSP56309 performs a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56309 provides the following peripherals: ¥...
Page 45: Host Interface (Hi08)
1.10.3 Enhanced Synchronous Serial Interface (ESSI) On the DSP56309 are two independent and identical ESSIs. Each ESSI has a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI.
Page 46: Timer Module
66 MHz clock). The asynchronous protocols supported by the SCI include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. This mode allows the DSP56309 to share a single serial line efficiently with other peripherals.
Page 47 DSP56309 Overview DSP56309 Architecture Overview 1-18 DSP56309UM/D MOTOROLA...
Page 48: Section 2 Signal/Connection Descriptions
SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS MOTOROLA DSP56309UM/D...
Page 49 TIMERS ........2-33 2.12 ONCE/JTAG INTERFACE......2-35 DSP56309UM/D MOTOROLA...
Page 50: Signal Groupings
Signal/Connection Descriptions Signal Groupings SIGNAL GROUPINGS The DSP56309 input and output signals are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. The DSP56309 is operated from a 3 V supply. Table 2-1 DSP56309 Functional Signal Groupings...
Page 51: Figure 2-1 Signals Identified By Functional Group
Signal/Connection Descriptions Signal Groupings After Reset During Reset DSP56309 MODA IRQA MODB IRQB MODC IRQC MODD IRQD Core Logic CCQL RESET RESET CCQH Host Interface (H108) Address Bus Non-Multiplexed Multiplexed Port B Data Bus GPIO Bus Control H0ÐH7 HAD0ÐHAD7 PB0ÐPB7...
Page 52: Power
Signal/Connection Descriptions Power POWER Power input descriptions for the DSP56309 are listed in Table 2-2. Table 2-2 Power Inputs Power Name Description PLL PowerÑV is power dedicated for phase-locked loop (PLL) use. The voltage should be well regulated, and the input should be provided with an extremely low impedance path to the V power rail.
Page 53: Ground
V connections are package-dependent. GROUND Ground descriptions for the DSP56309 are listed in Table 2-3. Table 2-3 Grounds Ground Name Description is a ground dedicated for PLL use. The connection PLL GroundÑGND...
Page 54: Clock
, to each other internally. On those packages, all ground connections, except GND , are labeled GND. The number of connections indicated in this table are minimum values; the total GND connections are package-dependent. CLOCK Clock Signal descriptions for the DSP56309 are listed in Table 2-4. Table 2-4 Clock Signals State Signal...
Page 55: Phase-Locked Loop (Pll)
If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. DSP56309UM/D MOTOROLA...
Page 56: External Memory Expansion Port (Port A)
(NMI) request internally synchronized to CLKOUT. EXTERNAL MEMORY EXPANSION PORT (PORT A) When the DSP56309 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A0ÐA17, D0ÐD23, AA0/RAS0ÐAA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
Page 57: External Data Bus
Otherwise, D0ÐD23 are weakly driven by the bus keeper. 2.6.3 External Bus Control External bus control signal descriptions for the DSP56309 are listed in Table 2-8. Table 2-8 External Bus Control Signals State Signal Type...
Page 58 Transfer AcknowledgeÑIf the DSP56309 is the bus Input master and there is no external bus activity, or the DSP56309 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely.
Page 59 DSP56309 is a bus master or a bus slave. Bus ÒparkingÓ allows BR to be deasserted even though the DSP56309 is the bus master; see the description of bus ÒparkingÓ in the BB signal description. The bus request hole...
Page 60 A0ÐA23 address lines. BCLK Output Tri-stated Bus Clock NotÑWhen the DSP is the bus master, BCLK is an active-low output and is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. MOTOROLA DSP56309UM/D 2-13...
Page 61: Interrupt And Mode Control
CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and IRQA is asserted, the processor exits the stop state. 2-14 DSP56309UM/D MOTOROLA...
Page 62 If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. MOTOROLA DSP56309UM/D 2-15...
Page 63: Host Interface (Hi08)
When reading multiple-bit registers that are written by another asynchronous system, you must synchronize carefully. This problem commonly occurs when two asynchronous systems are connected (as they are in the host port). The considerations for proper operation are discussed in Table 2-10. 2-16 DSP56309UM/D MOTOROLA...
Page 64: Host Port Configuration
HI08 Port Control Register (HPCR). Refer to Section 6ÑHost Interface (HI08) for detailed descriptions of this and the other configuration registers used with the HI08. Host interface signal descriptions for the DSP56309 are listed in Table 2-11. MOTOROLA DSP56309UM/D...
Page 65: Table 2-11 Host Interface
(HAS) following reset. Input or Port B 8ÑWhen the HI08 is configured as Output GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. 2-18 DSP56309UM/D MOTOROLA...
Page 66 HI function is selected, this signal is line 9 of the host address (HA9) input bus. PB10 Input or Port B 10ÑWhen the HI08 is configured as Output GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. MOTOROLA DSP56309UM/D 2-19...
Page 67 Input or active-low (HWR) following reset. PB12 Output Port B 12ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. 2-20 DSP56309UM/D MOTOROLA...
Page 68 10 of the host address (HA10) input bus. PB13 Input or Output Port B 13ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. MOTOROLA DSP56309UM/D 2-21...
Page 69 Port B 14ÑWhen the HI08 is programmed to Output interface a multiplexed host bus and the signal is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. 2-22 DSP56309UM/D MOTOROLA...
Page 70 Input or PB15 Output Port B 15ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. MOTOROLA DSP56309UM/D 2-23...
Page 71: Enhanced Synchronous Serial Interface
DSPs, microprocessors, and peripherals which implement the Motorola SPI. 2.9.1 ESSI0 The ESSI0 signal descriptions for the DSP56309 are listed in Table 2-12. Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) State Signal Type...
Page 72 Port C 2ÑThe default configuration Output following reset is GPIO input PC2. When this port is configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. MOTOROLA DSP56309UM/D 2-25...
Page 73 Port C 4ÑThe default configuration Output following reset is GPIO input PC4. When this port is configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. 2-26 DSP56309UM/D MOTOROLA...
Page 74: Essi1
PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. 2.9.2 ESSI1 The ESSI1 signal descriptions for the DSP56309 are listed in Table 2-13. MOTOROLA DSP56309UM/D 2-27...
Page 75: Table 2-13 Enhanced Synchronous Serial Interface 1 (Essi1)
Port D 1ÑThe default configuration Output following reset is GPIO input PD1. When this port is configured as PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1. 2-28 DSP56309UM/D MOTOROLA...
Page 76 Output Port D 2ÑThe default configuration following reset is GPIO input PD2. When this port is configured as PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. MOTOROLA DSP56309UM/D 2-29...
Page 77 Port D 4ÑThe default configuration Output following reset is GPIO input PD4. When this port is configured as PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. 2-30 DSP56309UM/D MOTOROLA...
Page 78 Port D 5ÑThe default configuration Output following reset is GPIO input PD5. When this port is configured as PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1. MOTOROLA DSP56309UM/D 2-31...
Page 79: Serial Communication Interface (Sci)
Port E 1ÑThe default configuration Output following reset is GPIO input PE1. When this port is configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. 2-32 DSP56309UM/D MOTOROLA...
Page 80: Timers
Three identical and independent timers are implemented in the DSP56309. Each timer can use internal or external clocking; each timer can interrupt the DSP56309 after a specified number of events (clocks) or can signal an external device after counting a specific number of internal events.
Page 81: Table 2-15 Triple Timer Signals
This signal is driven by a weak keeper after reset. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1 control/status register (TCSR1). 2-34 DSP56309UM/D MOTOROLA...
Page 82: Once/Jtag Interface
Input Input Test Data InputÑTDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. MOTOROLA DSP56309UM/D 2-35...
Page 83 TCK and has an internal pull-up resistor. TRST Input Input Test ResetÑTRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up. 2-36 DSP56309UM/D MOTOROLA...
Page 84 The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered debug mode. All other interfacing with the OnCE module must occur through the JTAG port. MOTOROLA DSP56309UM/D 2-37...
Page 85 Signal/Connection Descriptions OnCE/JTAG Interface 2-38 DSP56309UM/D MOTOROLA...
Page 86: Section 3 Memory Configuration
SECTION 3 MEMORY CONFIGURATION MOTOROLA DSP56309UM/D...
Page 87 MEMORY MAPS ........3-9 INTERNAL I/O MEMORY MAP ..... . 3-18 DSP56309UM/D MOTOROLA...
Page 88: Memory Spaces
(24-bit) program and data word; it ignores the zeroed byte, thus effectively using 16-bit program and data words. The sixteen-bit compatibility mode allows the DSP56309 to use 56000 object code without change, thus minimizing system cost for applications that use the smaller address space.
Page 89: Data Memory Space
Memory Configuration Memory Spaces DSP56309 to feed two operands to the Data ALU simultaneously, enabling it to perform a multiply-accumulate operation in one clock cycle. X and Y data memory are identical in structure and functionality except for the upper 128 words of each space.
Page 90: Memory Space Configuration
RAM Configuration 3.1.3 Memory Space Configuration Memory space addressing is 24-bit by default. The DSP56309 switches to sixteen-bit address compatibility mode by setting the sixteen-bit compatibility (SC) bit in the Status Register (SR). Table 3-1 Memory Space Configuration Bit Settings for the DSP56309...
Page 91: On-Chip Program Memory (Program Ram)
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can be switched from the X data RAM to the Program RAM by setting the MS bit (leaving 5K of X data RAM). DSP56309UM/D MOTOROLA...
Page 92: On-Chip Y Data Memory (Y Data Ram)
Program RAM, data RAM, and the instruction cache. 3.3.1 Memory Space Configurations The memory space configurations are listed in Table 3-3. Table 3-3 Memory Space Configurations for the DSP56309 SC Bit Addressable Number of Address Range...
Page 93: Ram Configurations
Memory Configuration Memory Configurations 3.3.2 RAM Configurations The RAM configurations for the DSP56309 appear in Table 3-4. Table 3-4 RAM Configurations for the DSP56309 Bit Settings Memory Sizes (in K) Program X data Y data Cache The actual memory locations for Program RAM and the instruction cache in the Program memory space are determined by the MS and CE bits.
Page 94: Memory Maps
Figure 3-1 through Figure 3-8 illustrate each of the memory space and RAM configurations defined by the settings of the SC, MS, and CE bits. The figures show the configuration, and the accompanying tables show the bit settings, memory sizes, and memory locations. MOTOROLA DSP56309UM/D...
Page 95: Figure 3-1 Default Settings (0, 0, 0)
Internal X data RAM Y data RAM $000000 $000000 $000000 Bit Settings Memory Configuration Program Addressable X Data RAM Y Data RAM Cache Memory Size None $0000Ð$4FFF $0000Ð$1BFF $0000Ð$1BFF AA0557 Figure 3-1 Default Settings (0, 0, 0) 3-10 DSP56309UM/D MOTOROLA...
Page 96: Figure 3-2 Instruction Cache Enabled (0, 0, 1)
Y data RAM $000000 $000000 $000000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size 16 M $0000Ð $0000Ð $0000Ð $4C00Ð $4BFF $1BFF $1BFF $4FFF AA0561 Figure 3-2 Instruction Cache Enabled (0, 0, 1) MOTOROLA DSP56309UM/D 3-11...
Page 97: Figure 3-3 Switched Program Ram (0, 1, 0)
Y data RAM Program RAM $000000 $000000 $000000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size None 16 M $0000Ð $0000Ð $0000Ð $5FFF $13FF $13FF AA0559 Figure 3-3 Switched Program RAM (0, 1, 0) 3-12 DSP56309UM/D MOTOROLA...
Page 98 $000000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size 16 M $0000Ð $0000Ð $0000Ð $5C00Ð $5BFF $13FF $13FF $5FFF AA0563 Figure 3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1) MOTOROLA DSP56309UM/D 3-13...
Page 99: Figure 3-5 16-Bit Space With Default Ram (1, 0, 0)
Y data RAM $0000 $0000 $0000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size None $0000Ð $0000Ð $0000Ð $4FFF $1BFF $1BFF AA0558 Figure 3-5 16-bit Space with Default RAM (1, 0, 0) 3-14 DSP56309UM/D MOTOROLA...
Page 100: Figure 3-6 16-Bit Space With Instruction Cache Enabled (1, 0, 1)
Y data RAM $0000 $0000 $0000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size $0000Ð $0000Ð $0000Ð $4C00Ð $4BFF $1BFF $1BFF $4FFF AA0562 Figure 3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1) MOTOROLA DSP56309UM/D 3-15...
Page 101: Figure 3-7 16-Bit Space With Switched Program Ram (1, 1, 0)
Program RAM $0000 $0000 $0000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size None $0000Ð $0000Ð $0000Ð $5FFF $13FF $13FF AA0560 Figure 3-7 16-bit Space with Switched Program RAM (1, 1, 0) 3-16 DSP56309UM/D MOTOROLA...
Page 102: Figure 3-8 16-Bit Space, Switched Program Ram, Instruction Cache
$0000 $0000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size $0000Ð $0000Ð $0000Ð $5C00Ð $5FFF $13FF $13FF $5FFF AA0564 Figure 3-8 16-bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) MOTOROLA DSP56309UM/D 3-17...
Page 103 Memory Configuration Internal I/O Memory Map INTERNAL I/O MEMORY MAP The DSP56309 internal X-I/O space (the top 128 locations of the X data memory space) is listed in Table D-2 on page D-11 of Appendix DÑInterrupt Sources. 3-18 DSP56309UM/D MOTOROLA...
Page 104: Core Configuration
SECTION 4 CORE CONFIGURATION MOTOROLA DSP56309UM/D...
Page 105 DEVICE IDENTIFICATION REGISTER (IDR)... 4-18 AA CONTROL REGISTERS (AAR0ÐAAR3) ... . 4-19 4.10 JTAG BOUNDARY SCAN REGISTER (BSR) ... 4-20 DSP56309UM/D MOTOROLA...
Page 106: Introduction
The DSP56309 begins operation by leaving Reset state and going into one of eight operating modes. As the DSP56309 exits the Reset state, it loads the values of MODA, MODB, MODC, and MODD into bits MA, MB, MC, and MD of the Operating Mode Register (OMR).
Page 107: Table 4-1 Dsp56309 Operating Modes
Core Configuration Bootstrap Program BOOTSTRAP PROGRAM Bootstrap operating mode descriptions for the DSP56309 are listed in Table 4-1. Table 4-1 DSP56309 Operating Modes Mode MODD MODC MODB MODA Reset Vector Description $C00000 Expanded mode: address $C00000 is reflected as $00000...
Page 108: Host Interface (Hi08)
$FF0000. If the bootstrap program is loading via the host interface (HI08), setting the HF0 bit in the host status register (HSR) causes the DSP56309 to stop loading and begin executing the loaded program at the specified start address.
Page 109 Vector $C00000 Expanded mode The bootstrap ROM is bypassed and the DSP56309 starts fetching instructions beginning at address $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected (by default). 4.3.2 Modes 1 to 7: Reserved These modes are reserved for future use.
Page 110 16 times the transmission data rate. Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter. 4.3.6 Mode B: Reserved Reset Mode MODD MODC MODB MODA Description Vector $FF0000 Reserved This mode is reserved for future use. MOTOROLA DSP56309UM/D...
Page 111 In mode D: boot from HI08 in HC11 non-multiplexed mode, the bootstrap program sets the host interface to interface with the Motorola HC11 microcontroller. If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program.
Page 112: Interrupt Sources And Priorities
INTERRUPT SOURCES AND PRIORITIES DSP56309 interrupt handling, like that of all DSP56300 family members, has been optimized for DSP applications. Refer to Section 7 of the DSP56300 Family Manual.
Page 113: Table 4-2 Interrupt Sources
The DSP56309 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions. In the DSP56309, only 46 of the 128 vector addresses are used for specific interrupt sources. The remaining 82 are reserved. If you know that certain interrupts will not be used, those interrupt vector locations can be used for program or data storage.
Page 114 SCI Idle Line VBA:$58 0Ð2 SCI Timer VBA:$5A 0Ð2 Reserved VBA:$5C 0Ð2 Reserved VBA:$5E 0Ð2 Reserved VBA:$60 0Ð2 Host Receive Data Full VBA:$62 0Ð2 Host Transmit Data Empty VBA:$64 0Ð2 Host Command (Default) VBA:$66 0Ð2 Reserved VBA:$FE 0Ð2 Reserved MOTOROLA DSP56309UM/D 4-11...
Page 115: Table 4-3 Interrupt Priority Level Bits
4.4.2 Interrupt Priority Levels The DSP56309 has a four-level interrupt priority structure. Each interrupt has two interrupt priority level bits (IPL[1:0]) that determine its interrupt priority level. Level 0 is the lowest priority; Level 3 is the highest-level priority and is non-maskable. Table 4-3 defines the IPL bits.
Page 116: Figure 4-1 Interrupt Priority Register C (Ipr-C) (X:$Ffffff)
Core Configuration Interrupt Sources and Priorities There are two interrupt priority registers in the DSP56309. The IPRÐC is dedicated to DSP56300 core interrupt sources, and IPRÐP is dedicated to DSP56309 peripheral interrupt sources. IPRÐC is shown in Figure 4-1 and IPRÐP is shown in Figure 4-2.
Page 117: Table 4-4 Interrupt Source Priorities Within An Ipl
IRQC (External Interrupt) Ñ IRQD (External Interrupt) Ñ DMA Channel 0 Interrupt Ñ DMA Channel 1 Interrupt Ñ DMA Channel 2 Interrupt Ñ DMA Channel 3 Interrupt Ñ DMA Channel 4 Interrupt Ñ DMA Channel 5 Interrupt 4-14 DSP56309UM/D MOTOROLA...
Page 118 SCI Receive Data With Exception Interrupt Ñ SCI Receive Data Ñ SCI Transmit Data Ñ SCI Idle Line Ñ SCI Timer Ñ TIMER0 Overflow Interrupt Ñ TIMER0 Compare Interrupt Ñ TIMER1 Overflow Interrupt Ñ TIMER1 Compare Interrupt MOTOROLA DSP56309UM/D 4-15...
Page 119: Table 4-5 Dma Request Sources
Transfer done from DMA channel 3 01000 Transfer done from DMA channel 4 01001 Transfer done from DMA channel 5 01010 ESSI0 Receive Data (RDF0 = 1) 01011 ESSI0 Transmit Data (TDE0 = 1) 01100 ESSI1 Receive Data (RDF1 = 1) 4-16 DSP56309UM/D MOTOROLA...
Page 120: Figure 4-3 Dsp56309 Operating Mode Register (Omr)
XYSÑStack Extension Space Select BEÑBurst Mode Enable MBÑOperating Mode B CDP1ÑCore-DMA Priority 1 MAÑOperating Mode A CDP0ÑCore-DMA Priority 0 - Reserved bit. Read as zero, should be written with zero for future compatibility. Figure 4-3 DSP56309 Operating Mode Register (OMR) MOTOROLA DSP56309UM/D 4-17...
Page 121: Figure 4-4 Pll Control (Pctl) Register
PCTL PLL Multiplication Factor Bits 0Ð11 The multiplication factor bits (MF[11:0]) define the Multiplication Factor (MF) that is applied to the PLL input frequency. The MF bits are cleared during a DSP56309 hardware reset, which corresponds to an MF of one.
Page 122: Figure 4-5 Identification Register Configuration (Revision 0)
DSP56309 (AAR0ÐAAR3), one for each AA signal. For a full description of the address attribute registers see the DSP56300 Family Manual Address multiplexing is not supported by the DSP56309. Bit 6 (BAM) of the AARs is reserved and should have only 0 written to it. MOTOROLA...
Page 123: Figure 4-6 Address Attribute Registers (Aar0Ðaar3)
4.10 JTAG BOUNDARY SCAN REGISTER (BSR) The BSR in the DSP56309 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All DSP56309 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR.
Page 124 SECTION 5 GENERAL-PURPOSE I/O MOTOROLA DSP56309UM/D...
Page 125 INTRODUCTION ........5-3 PROGRAMMING MODEL ......5-3 DSP56309UM/D MOTOROLA...
Page 126: Enhanced Synchronous Serial Interface
Introduction INTRODUCTION The DSP56309 provides thirty-four bidirectional signals that can be configured as GPIO signals or as dedicated peripheral signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The control register settings of the DSP56309Õs peripherals determine whether these signals function as GPIO or as...
Page 127: Serial Communication Interface (Sci)
Each of the three triple timer interface signals (TIO0ÐTIO2) not used as a timer signal can be configured as a GPIO signal. Each signal is controlled by the appropriate timer control status register (TCSR0ÐTCSR2). These registers are documented in Section 9ÑTriple Timer Module of this manual. DSP56309UM/D MOTOROLA...
Page 128 SECTION 6 HOST INTERFACE (HI08) MOTOROLA DSP56309UM/D...
Page 129 HI08-EXTERNAL HOST PROGRAMMERÕS MODEL ..6-20 SERVICING THE HOST INTERFACE ....6-31 HI08 PROGRAMMING MODEL QUICK REFERENCE..6-34 DSP56309UM/D MOTOROLA...
Page 130: Introduction
Host to DSP Core Interface ¥ Mapping: Ð Registers are directly mapped into eight internal X data memory locations ¥ Data word: Ð DSP56309 24-bit (native) data words are supported, as are 8-bit and 16-bit words ¥ Transfer modes: Ð DSP-to-host Ð...
Page 131 Ð Core DMA accesses ¥ Instructions: Ð Memory-mapped registers allow the standard MOVE instruction to be used to transfer data between the DSP56309 and external hosts. Ð Special MOVEP instruction provides for I/O service capability using fast interrupts. Ð Bit addressing instructions (e.g., BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines.
Page 132 Ð Glueless interface (no external logic required) to these devices: ¥ Motorola HC11 ¥ Hitachi H8 ¥ 8051 family ¥ Thomson P6 family Ð Minimal glue-logic (pullups, pulldowns) required to interface these devices: ¥ ISA bus ¥ Motorola 68K family Ò ¥ Intel X86 family MOTOROLA DSP56309UM/D...
Page 133: Table 6-1 Hi08 Signal Definitions For Various Operational Modes
Dual Strobe Bus GPIO Mode Signal HRW/HRD HRD/HRD PB11 HDS/HWR HDS/HDS HWR/HWR PB12 Table 6-3 HI08 Host Request Signals HI08 Port Vector Required No Vector Required GPIO Mode Signal HREQ/ HREQ/HREQ HTRQ/HTRQ PB14 HTRQ HACK/ HACK/HACK HRRQ/HRRQ PB15 HRRQ DSP56309UM/D MOTOROLA...
Page 134: Figure 6-1 Hi08 Block Diagram
RXL = Receive Register Low ISR = Interface Status Register TXH = Transmit Register High IVR = Interrupt Vector Register TXM = Transmit Register Middle RXH = Receive Register High TXL = Transmit Register High AA0657 Figure 6-1 HI08 Block Diagram MOTOROLA DSP56309UM/D...
Page 135: Hi08 Dsp Side Programmerõs Model
¥ Host data transmit register (HTX) The DSP side control registers are 16-bit registers that control DSP functions. The eight MSBs in the DSP side control registers are read by the DSP56309 as 0. Those registers are as follows: ¥ Host control register (HCR) ¥...
Page 136: Figure 6-2 Host Control Register (Hcr) (X:$Ffffc2)
The transfer operation sets both the TXDE and HRDF bits. When the HRDF bit is set, the HRX register contains valid data. The DSP56309 sets the HRIE bit (HCR, bit 0) to cause a host receive data interrupt when HRDF is set. When the DSP56309 reads the HRX register, the HRDF bit is cleared.
Page 137: Table 6-4 Host Command Interrupt Priority List
These two flags can be used individually or as encoded pairs in a simple DSP-to-host communication protocol, implemented in both the DSP and the host processor software. 6.5.3.5 HCR Reserved Bits 5-15 These bits are reserved. They are read as 0 and should be written with 0. 6-10 DSP56309UM/D MOTOROLA...
Page 138: Figure 6-3 Host Status Register (Hsr) (X:$Ffffc3)
ICR on the host side. They can be used individually or as encoded pairs in a simple host-to-DSP communication protocol implemented in both the DSP and the host processor software. 6.5.4.5 HSR Reserved Bits 5-15 These bits are reserved. They are read as 0 and should be written with 0. MOTOROLA DSP56309UM/D 6-11...
Page 139: Figure 6-4 Host Base Address Register (Hbar) (X:$Ffffc5)
Reserved bits are read as 0 and should be written with 0 for future compatibility. The initialization values for the HPCR bits are described in Section 6.5.9ÑDSP Side Registers After Reset. The HPCR bits are illustrated in Figure 6-6. 6-12 DSP56309UM/D MOTOROLA...
Page 140: Figure 6-6 Host Port Control Register (Hpcr) (X:$Ffffc4)
AA0660 Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4) Note: To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP,...
Page 141 If HDSP is set, the data strobe signals are configured as active high inputs, and data is transferred when the data strobe is high. The data strobe signals are either HDS by itself or both HRD and HWR together. 6-14 DSP56309UM/D MOTOROLA...
Page 142: Figure 6-7 Single Strobe Bus
See Figure 6-7 and Figure 6-8 for more information on the two types of buses. In a single-strobe bus, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write) signal specifies the direction of the access. AA0661 Figure 6-7 Single Strobe Bus MOTOROLA DSP56309UM/D 6-15...
Page 143: Figure 6-8 Dual Strobe Bus
The HI08 drives the contents of the IVR onto the host bus when the HACK signal is low. If the HAP bit is set, the HACK signal is configured as an active high input. The HI08 outputs the contents of the IVR when the HACK signal is high. 6-16 DSP56309UM/D MOTOROLA...
Page 144: Figure 6-9 Host Data Direction Register (Hddr) (X:$Ffffc8)
GPIO signals. It is illustrated in Figure 6-10. The functionality of the Dxx bit depends on the corresponding HDDR bit (DRxx), as in Table 6-5. The HDR cannot be accessed by the host processor. AA0664 Figure 6-10 Host Data Register (HDR) (X:$FFFFC9) MOTOROLA DSP56309UM/D 6-17...
Page 145: Table 6-5 Hdr And Hddr Functionality
DSP Side Registers After Reset Table 6-6 shows the results of the four reset types on the bits in each of the HI08 registers accessible by the DSP56309. Reset types are as follows: ¥ Hardware reset (HW) caused by the RESET signal Ñ...
Page 146: Table 6-6 Dsp Side Registers After Reset
The HI08 can request interrupt service from either the DSP56309 or the host processor. The DSP56309 interrupts are internal and do not require the use of an external interrupt signal. When the appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host processor sets the appropriate bit in the HSR, generating an interrupt request to the DSP56309.
Page 147: Figure 6-11 Hsr-Hcr Operation
HI08-External Host ProgrammerÕs Model routine must read or write the appropriate HI08 register (e.g., clearing HRDF or HTDE) to clear the interrupt. For host command interrupts, the interrupt acknowledge from the DSP56309 program controller clears the pending interrupt condition. Enable X:HCR...
Page 148 I/O instruction rate without testing the handshake flags for each transfer. If full handshake is not needed, the host processor can treat the DSP56309 as a fast device, and data can be transferred between the host processor and the DSP56309 at the fastest host processor data rate.
Page 149: Figure 6-12 Interface Control Register
The control bits are described in the following paragraphs. INIT HLEND HDRQ TREQ RREQ ÑReserved bit. Read as 0. Should be written with 0, for future compatibility. AA0668 Figure 6-12 Interface Control Register 6-22 DSP56309UM/D MOTOROLA...
Page 150: Table 6-8 Treq And Rreq Modes (Hdrq = 0)
RXDF Request (Interrupt) 6.6.1.3 ICR Double Host Request (HDRQ) Bit 2 If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ and HACK/HRRQ are configured as HTRQ and HRRQ, respectively. MOTOROLA DSP56309UM/D 6-23...
Page 151 ICR Host Flag 0 (HF0) Bit 3 The HF0 bit is a general-purpose flag for host-to-DSP communication. The host processor can set or clear HF0, and the DSP56309 cannot change this bit. HF0 is reflected in the HSR on the DSP side of the HI08.
Page 152: Figure 6-13 Command Vector Register (Cvr)
6.6.2 Command Vector Register (CVR) The host processor uses the CVR to cause the DSP56309 to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI08. It can cause any of the 128 possible interrupt routines in the DSP core to be executed. This register is illustrated in Figure 6-13.
Page 153: Figure 6-14 Interface Status Register
The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP56309 and can be read by the host processor. RXDF is set when the HTX is transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to HLEND bit) register is read by the host processor.
Page 154 DSP side of the HI08. This feature has many applications. For example, if the host processor issues a host command which causes the DSP56309 to read the HRX, the host processor can be guaranteed that the data it just transferred to the HI08 is that being received by the DSP56309.
Page 155: Figure 6-15 Interrupt Vector Register (Ivr)
The receive byte registers are viewed by the host processor as three 8-bit, read-only registers. These registers are the receive high register (RXH), the receive middle register (RXM), and the receive low register (RXL). They receive data from the high, middle, and 6-28 DSP56309UM/D MOTOROLA...
Page 156 If you read any of those status bits within the next two cycles, the bit does not reflect its current status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral Device for Write for further details. MOTOROLA DSP56309UM/D 6-29...
Page 157: Table 6-12 Host Side Registers After Reset
6.6.8 General-Purpose I/O When configured as GPIO, the HI08 is viewed by the DSP56309 as memory-mapped registers, as documented in Section 6.5ÑHI08 DSP Side ProgrammerÕs Model on page 6-8. Those memory-mapped registers control up to 16 I/O signals. Software RESET instructions and hardware RESET signals clear all DSP side control registers and configure the HI08 as GPIO with all 16 signals disconnected.
Page 158: Servicing The Host Interface
HACK must be deasserted to insure IVR data is not being driven on H[7:0] when other registers are being polled. (If the HACK function is not needed, the HACK signal can be configured as a GPIO signal, as documented in Section 6.5.6ÑHost Port Control Register (HPCR) on page 6-12.) MOTOROLA DSP56309UM/D 6-31...
Page 159 If the host processor has issued a command to the DSP56309 by writing to the CVR and setting the HC bit, it can read the HC bit in the CVR to determine whether the command has been accepted by the interrupt controller in the DSP core.
Page 160: Figure 6-16 Hi08 Host Request Structure
HACK. The contents of the IVR are placed on the host data bus while HREQ/TRQ (or HRRQ) and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP56309. Table 6-13 shows the HI08 programming model.
Page 161: Hi08 Programming Model Quick Reference
Host Interface (HI08) HI08 Programming Model Quick Reference 6-34 DSP56309UM/D MOTOROLA...
Page 162 Host Interface (HI08) HI08 Programming Model Quick Reference MOTOROLA DSP56309UM/D 6-35...
Page 163 Host Interface (HI08) HI08 Programming Model Quick Reference 6-36 DSP56309UM/D MOTOROLA...
Page 164 Host Interface (HI08) HI08 Programming Model Quick Reference MOTOROLA DSP56309UM/D 6-37...
Page 165 Host Interface (HI08) HI08 Programming Model Quick Reference 6-38 DSP56309UM/D MOTOROLA...
Page 166 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) MOTOROLA DSP56309UM/D...
Page 167 OPERATING MODES ......7-36 GPIO SIGNALS AND REGISTERS....7-43 DSP56309UM/D MOTOROLA...
Page 168 Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. There are two independent and identical ESSIs in the DSP56309: ESSI0 and ESSI1. For the sake of simplicity, a single generic ESSI is described.
Page 169 The SRD signal receives serial data and transfers the data to the ESSI receive shift register. SRD can be programmed as a GPIO signal (P4) when the ESSI SRD function is not being used. The ESSI block diagram is shown in Figure 7-1. DSP56309UM/D MOTOROLA...
Page 170: Figure 7-1 Essi Block Diagram
The SCK signal is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The SCK signal is a clock input or output used by all the enabled transmitters and receiver in synchronous modes or by all the enabled transmitters in asynchronous MOTOROLA DSP56309UM/D...
Page 171 SCD0. SC0 can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not being used. Note: The ESSI can operate with more than one active transmitter only in synchronous mode. DSP56309UM/D MOTOROLA...
Page 172 SCD1. SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1 function is not being used. Table 7-1 summarizes ESSI clock sources, whether synchronous or asynchronous, and shows the bit settings for the signals involved. MOTOROLA DSP56309UM/D...
Page 173: Table 7-1 Essi Clock Sources
GPIO signal (P2) when the ESSI SC2 function is not being used. ESSI PROGRAMMING MODEL The ESSI includes the following registers: ¥ Two control registers (CRA, CRB) illustrated in Figure 7-2 and Figure 7-3 ¥ One status register (SSISR) illustrated in Figure 7-4 DSP56309UM/D MOTOROLA...
Page 174: Figure 7-2 Essi Control Register A (Cra)
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5) FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 REIE TEIE RLIE TLIE AA0858 Figure 7-3 ESSI Control Register B (CRB) (ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6) AA0859 Figure 7-4 ESSI Status Register (SSISR) (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7) MOTOROLA DSP56309UM/D...
Page 175: Figure 7-5 Essi Transmit Slot Mask Register A (Tsma)
RS19 RS18 RS17 RS16 RS31 RS30 RS29 RS28 Ð Reserved bit - read as zero should be written with zero for future compatibility AA0863 Figure 7-8 ESSI Receive Slot Mask Register B (RSMB) (ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1) 7-10 DSP56309UM/D MOTOROLA...
Page 176 The maximum allowed internally generated bit clock frequency is the internal DSP56309 clock frequency divided by 4; the minimum possible internally generated bit clock frequency is the DSP56309 internal clock frequency divided by 4096. Both the hardware RESET signal and the software RESET instruction clear PSR.
Page 177: Figure 7-9 Essi Clock Generator Functional Block Diagram
FSL[1:0] bits in the CRA to (01). Both the hardware RESET signal and the software RESET instruction clear DC[4:0]. The ESSI frame sync generator functional diagram is shown in Figure 7-10. 7-12 DSP56309UM/D MOTOROLA...
Page 178: Figure 7-10 Essi Frame Sync Generator Functional Block Diagram
23 in the transmit shift register. The ALC bit is cleared by either a hardware RESET signal or a software RESET instruction. Note: If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of 24- or 32-bit words leads to unpredictable results. MOTOROLA DSP56309UM/D 7-13...
Page 179: Table 7-2 Essi Word Length Selection
0. This enables an external buffer for the transmitter 0 output. If SSC1 is cleared, SC1 acts as the serial I/O flag. 7.4.1.9 CRA Reserved Bit 23 This bit is reserved. It is read as 0 and should be written with 0. 7-14 DSP56309UM/D MOTOROLA...
Page 180 ESSI flag 0. If the serial control direction bit (SCD0) is set, the SC0 signal is an output. Data present in bit OF0 is written to SC0 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. MOTOROLA DSP56309UM/D 7-15...
Page 181 When SCKD is cleared, the external clock source is selected. The internal clock generator is disconnected from the SCK signal, and an external clock source can drive this signal. Either a hardware RESET signal or a software RESET instruction clears SCKD. 7-16 DSP56309UM/D MOTOROLA...
Page 182: Table 7-3 Fsl1 And Fsl0 Encoding
CRB Frame Sync Polarity (FSP) Bit 10 The FSP bit determines the polarity of the receive and transmit frame sync signals. When FSP is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated MOTOROLA DSP56309UM/D 7-17...
Page 183 ESSI is in synchronous mode and the transmit and receive sections use common clock and frame sync signals. Only in synchronous mode can more than one transmitter be enabled. Either a hardware RESET signal or a software RESET instruction clears SYN. 7-18 DSP56309UM/D MOTOROLA...
Page 184: Figure 7-11 Crb Fsl0 And Fsl1 Bit Operation (Fsr = 0)
Mixed Frame Length: FSL1 = 1, FSL0 = 1 Serial Clock RX Frame SYNC RX Serial Data Data Data TX Frame SYNC TX Serial Data Data Data AA0681 Figure 7-11 CRB FSL0 and FSL1 Bit Operation (FSR = 0) MOTOROLA DSP56309UM/D 7-19...
Page 185: Figure 7-12 Crb Syn Bit Operation
SYNC Clock External Clock External Frame SYNC Internal Clock Internal Frame SYNC ESSI Bit Clock Clock Frame SYNC Receiver NOTE: Transmitter and receiver can have the same clock frame syncs. AA0682 Figure 7-12 CRB SYN Bit Operation 7-20 DSP56309UM/D MOTOROLA...
Page 186 Enhanced Synchronous Serial Interface (ESSI) ESSI Programming Model MOTOROLA DSP56309UM/D 7-21...
Page 187: Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word In Frame)
ESSI transmit shift register. Any data present in TX2 is not transmitted. If TE2 is cleared, data can be written to TX2; the TDE bit is cleared, but data is not transferred to transmit shift register 2. 7-22 DSP56309UM/D MOTOROLA...
Page 188: Figure 7-15 Network Mode, External Frame Sync (8 Bit, 2 Words In Frame)
I/O flag from the start of the frame, in both normal and network mode. The transmit enable sequence for on-demand mode can be the same as for normal mode, or the TE1 bit can be left enabled. MOTOROLA DSP56309UM/D 7-23...
Page 189: Table 7-4 Mode And Signal Definition Table
(SYN = 0). TE0 does not affect the generation of frame sync or output flags. Table 7-4 summarizes the preceding sections; it shows possible settings of control bits and their associated signals. Table 7-4 Mode and Signal Definition Table Control Bits ESSI Signals 7-24 DSP56309UM/D MOTOROLA...
Page 190 Transmit Data signal 2 Note: Transmitter 0 drive enable if SSC1 = 1 & SCD1 = 1 Note: Receive Data Note: Flag 0 Note: Flag 1 if SSC1 = 0 Note: Unused (can be used as GPIO signal) Note: Indeterminate MOTOROLA DSP56309UM/D 7-25...
Page 191 Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when the ESSI is in network mode. When TLIE is set, the DSP is interrupted at the start of the last slot in a frame regardless of the transmit mask register setting. When TLIE is cleared, 7-26 DSP56309UM/D MOTOROLA...
Page 192 The SSISR (in Figure 7-4 on page 7-9) is a 24-bit, read-only status register used by the DSP to read the status and serial input flags of the ESSI. The SSISR bits are documented in the following paragraphs. MOTOROLA DSP56309UM/D 7-27...
Page 193 SSISR Receive Frame Sync Flag (RFS) Bit 3 When set, the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register. This means that the data word is from the 7-28 DSP56309UM/D MOTOROLA...
Page 194 TSR. The TDE bit is cleared when the DSP56309 writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot. If the TIE bit is set, a DSP transmit data interrupt request is issued when TDE is set.
Page 195 If RIE is set, a DSP receive data interrupt request is issued when RDF is set. A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the RDF bit. The ESSI data path programming models are shown in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. 7-30 DSP56309UM/D MOTOROLA...
Page 196: Figure 7-16 Essi Data Path Programming Model (Shfd = 0)
24-bit Data NOTES: (b) Transmit Registers Data is transmitted MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. AA0686 Figure 7-16 ESSI Data Path Programming Model (SHFD = 0) MOTOROLA DSP56309UM/D 7-31...
Page 197: Figure 7-17 Essi Data Path Programming Model (Shfd = 1)
24-bit Data NOTES: (b) Transmit Registers Data is received MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. AA0687 Figure 7-17 ESSI Data Path Programming Model (SHFD = 1) 7-32 DSP56309UM/D MOTOROLA...
Page 198 MSB is bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the SHFD bit is set. MOTOROLA DSP56309UM/D 7-33...
Page 199 Depending on the setting of the bits, the transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data word and generate a transmitter empty condition. 7-34 DSP56309UM/D MOTOROLA...
Page 200 N, and the RDF flag is set. Setting the bits in the RSM affects the next frame transmission. The frame currently being transmitted is not affected by the new RSM setting. If the RSM is read, it shows the current setting. MOTOROLA DSP56309UM/D 7-35...
Page 201 All status bits of the interface are set to their reset state. The contents of CRA and CRB are not affected. The ESSI individual reset allows a program to reset each interface separately from the other 7-36 DSP56309UM/D MOTOROLA...
Page 202 Occurs when the receive exception interrupt is enabled, the receive data register is full, and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE bit is cleared by first reading the SSISR and then reading RX. MOTOROLA DSP56309UM/D 7-37...
Page 203 TX registers or to the TSR clears this interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead (if no more than two transmitters are used). To configure an ESSI exception, perform the following steps: 7-38 DSP56309UM/D MOTOROLA...
Page 204 (the event is not queued in this case). 6. If interrupts derived from the core or other peripherals need to be enabled at the same time as ESSI interrupts, step f should be done last. MOTOROLA DSP56309UM/D 7-39...
Page 205 SYN bit is set, the ESSI TX and RX clocks and frame sync are driven by the same source (either external or internal). Since the ESSI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. 7-40 DSP56309UM/D MOTOROLA...
Page 206 ¥ If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data transfer period. This frame sync length is compatible with Motorola codecs, serial peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift registers, and telecommunication pulse code modulation (PCM) serial I/O.
Page 207 Two ESSI signals (SC[1:0]) are available for use as serial I/O flags. Their operation is controlled by the SYN, SCD[1:0], SSC1, and TE[2:1] bits in the CRB/CRA.The control bits OF[1:0] and status bits IF[1:0] are double-buffered to/from SC[1:0]. Double-buffering the flags keeps the flags in sync with TX and RX. 7-42 DSP56309UM/D MOTOROLA...
Page 208 The OF[1:0] values can be set directly by software. This allows the DSP56309 to control data transmission by indirectly controlling the value of the SC[1:0] flags.
Page 209: Figure 7-18 Port Control Register (Pcr) (Pcrc X:$Ffffbf)
PDC3 PDC2 PDC1 PDC0 STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PRRC: ESSI0, PRRD: ESSI1 Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0689 Figure 7-19 Port Direction Register (PRR)(PRRC X:$FFFFBE) (PRRD X:$FFFFAE) 7-44 DSP56309UM/D MOTOROLA...
Page 210: Figure 7-20 Port Data Register (Pdr) (Pdrc X:$Ffffbd)
PD[i] bit is reflected on the this signal. Figure 7-20 shows the PDR bits. STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PDRD: ESSI0, PDRD: ESSI1 Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility AA0690 Figure 7-20 Port Data Register (PDR) (PDRC X:$FFFFBD) (PDRD X:$FFFFAD) MOTOROLA DSP56309UM/D 7-45...
Page 211 Enhanced Synchronous Serial Interface (ESSI) GPIO Signals and Registers Note: Either a hardware RESET signal or a software RESET instruction clears all PDR bits. 7-46 DSP56309UM/D MOTOROLA...
Page 212 SECTION 8 SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA DSP56309UM/D...
Page 213 OPERATING MODES ......8-21 GPIO SIGNALS AND REGISTERS....8-27 DSP56309UM/D MOTOROLA...
Page 214 Serial Communication Interface (SCI) Introduction INTRODUCTION The DSP56309 serial communication interface (SCI) provides a full-duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as the RS232C, RS422, etc.
Page 215 The SCI programming model can be viewed as three types of registers: ¥ Control Ð SCI control register (SCR) in Figure 8-1 Ð SCI clock control register (SCCR) in Figure 8-3 ¥ Status Ð SCI status register (SSR) in Figure 8-2 ¥ Data transfer DSP56309UM/D MOTOROLA...
Page 216: Figure 8-1 Sci Control Register (Scr)
Figure 8-1 SCI Control Register (SCR) IDLE RDRF TDRE TRNE AA0855 Figure 8-2 SCI Status Register (SSR) CD11 CD10 Reserved bit - read as 0 should be written with 0 for future compatibility AA0856 Figure 8-3 SCI Clock Control Register (SCCR) MOTOROLA DSP56309UM/D...
Page 217: Figure 8-4 Sci Data Word Formats
Note: 1. Modes 1, 3, and 7 are reserved. 0 = Data Byte 2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 AA0691 Figure 8-4 SCI Data Word Formats DSP56309UM/D MOTOROLA...
Page 218 0 = Data Byte 2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 AA0691 (cont.) Figure 8-4 SCI Data Word Formats (Continued) MOTOROLA DSP56309UM/D...
Page 219: Table 8-1 Word Formats
1s, an error in transmission has occurred. When even parity is selected, an even number must result from the calculation performed at both ends of the line, or an error in transmission has occurred. DSP56309UM/D MOTOROLA...
Page 220 When RWU is set and the SCI is in an asynchronous mode, the wakeup function is enabledÑthat is, the SCI is asleep, and can be awakened by the event defined by the WAKE bit. In the sleep state, all interrupts and all receive flags except IDLE are disabled. MOTOROLA DSP56309UM/D...
Page 221 8.3.1.8 SCR Transmitter Enable (TE) Bit 9 When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes transmission of data in the SCI Transmit Data Shift Register, then the serial output is 8-10 DSP56309UM/D MOTOROLA...
Page 222 SCR SCI Receive Interrupt Enable (RIE) Bit 11 The RIE bit is set to enable the SCI Receive Data interrupt. If RIE is cleared, the Receive Data interrupt is disabled, and then the RDRF bit in the SCI Status Register must be MOTOROLA DSP56309UM/D 8-11...
Page 223 In asynchronous mode, positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid. Negative polarity means that the falling edge of the clock occurs during the center of the period 8-12 DSP56309UM/D MOTOROLA...
Page 224 4 serial clock cycle delay between writing STX and loading the transmit shift register; in addition, TDRE is set in the middle of transmitting the second bit. When using an external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE is not set MOTOROLA DSP56309UM/D 8-13...
Page 225 10-bit asynchronous mode, 11-bit multidrop mode, and 8-bit synchronous mode, the PE bit is always cleared since there is no parity bit in these modes. If the byte received causes both parity and overrun errors, the SCI receiver recognizes only the overrun error. 8-14 DSP56309UM/D MOTOROLA...
Page 226: Figure 8-3 Sci Clock Control Register (Sccr)
SCKP is set, the data changes on the positive edge and is stable on the negative edge. ¥ The received data on the RXD signal is sampled on the positive edge (if SCKP = 0) ´ or on the negative edge (if SCKP = 1) of the 1 serial clock. MOTOROLA DSP56309UM/D 8-15...
Page 227: Figure 8-5 16 X Serial Clock
¥ If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK ´ signal. Thus, the SCLK output is a 16 baud clock. Either a hardware RESET signal or a software RESET instruction clears COD. 8-16 DSP56309UM/D MOTOROLA...
Page 228: Table 8-2 Tcm And Rcm Bit Configuration
Either a hardware RESET signal or a software RESET instruction clears RCM. Table 8-2 TCM and RCM Bit Configuration SCLK TX Clock RX Clock Mode Signal Internal Internal Output Synchronous/Asynchronous Internal External Input Asynchronous Only External Internal Input Asynchronous Only External External Input Synchronous/Asynchronous MOTOROLA DSP56309UM/D 8-17...
Page 229: Figure 8-6 Sci Baud Rate Generator
Figure 8-7). There are two receive registersÑa receive data register (SRX) and a serial-to-parallel receive shift register. There are also two transmit registersÑa transmit data register (called either STX or STXA) and a parallel-to-serial transmit shift register. 8-18 DSP56309UM/D MOTOROLA...
Page 230: Figure 8-7 Sci Programming Model Data Registers
0s. Mapping SRX as described allows three bytes to be efficiently packed into one 24-bit word by ORing three data bytes read from the three addresses. MOTOROLA DSP56309UM/D 8-19...
Page 231 STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either STX or STXA is usually written as part of the interrupt service routine. An interrupt is generated only if TDRE is set. The transmit shift register is indirectly visible via the TRNE bit in the SSR. 8-20 DSP56309UM/D MOTOROLA...
Page 232 ¥ 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop) This mode is used for master/slave operation with wakeup on idle line and wakeup on address bit capability. It allows the DSP56309 to share a single serial line efficiently with other peripherals.
Page 233 Executing the STOP instruction halts operation of the SCI until the DSP is restarted, causing the SSR to be reset. No other SCI registers are affected by the STOP instruction. Table 8-3 on page 8-23 illustrates how each type of reset affects each register in the SCI. 8-22 DSP56309UM/D MOTOROLA...
Page 234: Table 8-3 Sci Registers After Reset
STIR Ñ Ñ TMIE Ñ Ñ Ñ Ñ Ñ Ñ ILIE Ñ Ñ Ñ Ñ Ñ Ñ WOMS Ñ Ñ Ñ Ñ WAKE Ñ Ñ Ñ Ñ SSFTD Ñ Ñ WDS[2:0] 2Ð0 Ñ Ñ IDLE RDRF TDRE MOTOROLA DSP56309UM/D 8-23...
Page 235 SCI Initialization The correct way to initialize the SCI is as follows: 1. Send a hardware RESET signal or software RESET instruction. 2. Program SCI control registers. 3. Configure at least one SCI signal as other than GPIO. 8-24 DSP56309UM/D MOTOROLA...
Page 236 SCI receive sequence on the RXD signal, as defined by the operating mode (i.e., idle line sequence). ¥ Data is transmitted only after the transmitter is enabled (TE = 1), and after transmitting the initialization sequence depending on the operating mode. MOTOROLA DSP56309UM/D 8-25...
Page 237 This interrupt is enabled by SCR bit 10 (ILIE). 5. SCI timer is caused by the baud rate counter reaching zero. This interrupt is automatically reset when the interrupt is accepted. This interrupt is enabled by SCR bit 13 (TMIE). 8-26 DSP56309UM/D MOTOROLA...
Page 238: Figure 8-8 Port E Control Register (Pcre)
GPIO, PDC[i] controls the port signal direction. When PDC[i] is set, the GPIO port signal[i] is configured as output. When PDC[i] is cleared, the GPIO port signal[i] is configured as input. Bits in the Port E direction register appear in Figure 8-9. MOTOROLA DSP56309UM/D 8-27...
Page 239: Figure 8-9 Port E Direction Register (Prre)
PD[i] bit reflects the value of this signal. If a port signal[i] is configured as a GPIO output, then the value of the corresponding PD[i] bit is reflected on this signal. Bits of the Port E data register appear in Figure 8-10. 8-28 DSP56309UM/D MOTOROLA...
Page 240: Figure 8-10 Port E Data Register (Pdre)
GPIO Signals and Registers Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility AA0697 Figure 8-10 Port E Data Register (PDRE) Note: A hardware RESET signal or a software RESET instruction clears all PDRE bits. MOTOROLA DSP56309UM/D 8-29...
Page 241 Serial Communication Interface (SCI) GPIO Signals and Registers 8-30 DSP56309UM/D MOTOROLA...
Page 242 SECTION 9 TRIPLE TIMER MODULE MOTOROLA DSP56309UM/D...
Page 243 TRIPLE TIMER MODULE ARCHITECTURE ... . 9-3 TRIPLE TIMER MODULE PROGRAMMING MODEL..9-5 TIMER OPERATIONAL MODES..... 9-16 DSP56309UM/D MOTOROLA...
Page 244: Introduction
Introduction INTRODUCTION This section describes the internal triple timer module in the DSP56309. Each timer has a single signal that can be used as a GPIO signal or as a timer signal. These three timers can be used to generate timed pulses or as pulse width modulators. They can also be used as an event counter, to capture an event, or to measure the width or period of a signal.
Page 245: Figure 9-1 Triple Timer Module Block Diagram
The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR). For a listing of the timer modes, see Section 9ÑTimer Operational Modes. For a description of their operation, see Section 9.4.1ÑTiming Modes. DSP56309UM/D MOTOROLA...
Page 246: Figure 9-2 Timer Module Block Diagram
Triple Timer Module Triple Timer Module Programming Model The DSP56309 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers. The timer programming model is shown in Figure 9-3 on page 9-6.
Page 247: Figure 9-3 Timer Module Programmerõs Model
TCPR1 = $FFFF89 TCPR2 = $FFFF85 Timer Count Register (TCR) TCR0 = $FFFF8C TCR1 = $FFFF88 TCR2 = $FFFF84 - reserved, read as 0, should be written with 0 for future compatibility Figure 9-3 Timer Module ProgrammerÕs Model DSP56309UM/D MOTOROLA...
Page 248: Figure 9-4 Timer Prescaler Load Register (Tplr)
The two PS bits control the source of the prescaler clock. Table 9-1 summarizes PS bit functionality. The prescalerÕs use of a TIO signal is not affected by the TCSR settings of the timer corresponding to the TIO signal being used. MOTOROLA DSP56309UM/D...
Page 249: Figure 9-5 Timer Prescaler Count Register (Tpcr)
If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56309 internal operating frequency divided by 4 (CLK/4).
Page 250: Figure 9-6 Timer Control/Status Register
The timer counter can hold a maximum value of $FFFFFF. When the counter value is at the maximum value and a new event causes the counter to be incremented to $000000, the timer generates an overflow interrupt. MOTOROLA DSP56309UM/D...
Page 251: Table 9-2 Timer Control Bits
(i.e., when the TE bit in the TCSR has been cleared). Table 9-2 Timer Control Bits Bit Settings Mode Characteristics Mode Mode Function Clock Number Timer and GPIO Internal GPIO Timer Pulse Output Internal Timer Toggle Output Internal Event Counter Input External 9-10 DSP56309UM/D MOTOROLA...
Page 252 The Inverter (INV) bit affects the polarity definition of the incoming signal on the TIO signal when TIO is programmed as input. It also affects the polarity of the output pulse generated on the TIO signal when TIO is programmed as output. MOTOROLA DSP56309UM/D 9-11...
Page 253: Table 9-3 Inverter (Inv) Bit Operation
Event is captured Event is captured Ñ Ñ on the rising edge on the falling of the signal from edge of the signal the TIO signal from the TIO signal 9-12 DSP56309UM/D MOTOROLA...
Page 254 TLR value on each appropriate edge of the input signal. If the TRM bit is cleared, the counter operates as a free running counter and is incremented on each incoming event. The TRM bit is cleared by a hardware RESET signal or a software RESET instruction. MOTOROLA DSP56309UM/D 9-13...
Page 255 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the timer overflow interrupt is serviced. The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer. 9-14 DSP56309UM/D MOTOROLA...
Page 256 In this mode, the counter is also reloaded whenever the TLR is written with a new value while the TE bit in the TCSR is set. ¥ In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as a free-running counter. MOTOROLA DSP56309UM/D 9-15...
Page 257: Timer Operational Modes
Ð Input width, mode 4: Input pulse width measurement Ð Input pulse, mode 5: Input signal period measurement Ð Capture, mode 6: Capture external signal ¥ PWM, mode 7: Pulse width modulation ¥ Watchdog Ð Pulse, mode 9: Output pulse, internal clock 9-16 DSP56309UM/D MOTOROLA...
Page 258 TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.
Page 259 The TIO signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.
Page 260 The TIO signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.
Page 261 Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock, and its frequency must be less than the DSP56309 internal operating frequency divided by 4.
Page 262 TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56309 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter.
Page 263 After the first appropriate transition occurs on the TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56309 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent clock signal increments the counter.
Page 264 TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.
Page 265 TPCR. When first timer clock is received from either the DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock increments the counter.
Page 266 TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter.
Page 267 TPCR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO signal is set to the value of the INV bit.
Page 268 TIO signals are disconnected. Any external changes that happen to the TIO signals are ignored when the DSP56309 is in the stop state. To insure correct operation, the timers should be disabled before the DSP56309 is placed into the stop state.
Page 269 Triple Timer Module Timer Operational Modes 9-28 DSP56309UM/D MOTOROLA...
Page 270: On-Chip Emulation Module
SECTION 10 ON-CHIP EMULATION MODULE MOTOROLA DSP56309UM/D 10-1...
Page 271: Jtag Port
ONCE MODULE EXAMPLES ..... . 10-23 10.13 JTAG PORT/ONCE MODULE INTERACTION ..10-29 10-2 DSP56309UM/D MOTOROLA...
Page 272: Figure 10-1 Once Module Block Diagram
TCK, TDI, and TDO are used to shift in and out data and instructions. See Section 11.2ÑJTAG Signals on page 11-4 for the description of the JTAG signals. To facilitate emulation-specific functions, one additional signal, called DE, is provided on the DSP56309. MOTOROLA DSP56309UM/D...
Page 273: Figure 10-2 Once Module Multiprocessor Configuration
The user can also stop all the devices synchronously by asserting the DE line. 10.4 OnCE CONTROLLER The OnCE controller contains the following blocks: OnCE Command Register (OCR), OnCE Decoder, and the status/control register. Figure 10-3 illustrates a block diagram of the OnCE controller. 10-4 DSP56309UM/D MOTOROLA...
Page 274: Figure 10-3 Once Controller Block Diagram
Exit Command (EX) Bit 5 If the EX bit is set, leave debug mode and resume normal operation. The EXIT command is executed only if the GO command is issued, and the operation is write to OPDBR or MOTOROLA DSP56309UM/D 10-5...
Page 275: Table 10-1 Ex Bit Definition
Write the data associated with the command into the register specified by RS4ÐRS0. Read the data contained in the register specified by RS4ÐRS0. Table 10-4 OnCE Register Select Encoding RS[4:0] Register Selected 00000 OnCE Status and Control Register (OSCR) 10-6 DSP56309UM/D MOTOROLA...
Page 276 10000 PAB Register for Decode (OPABDR) 10001 PAB Register for Execute (OPABEX) 10010 Trace Buffer and Increment Pointer 10011 Reserved Address 101xx Reserved Address 11xx0 Reserved Address 11x0x Reserved Address 110xx Reserved Address 11111 No Register Selected MOTOROLA DSP56309UM/D 10-7...
Page 277: Figure 10-5 Once Status And Control Register (Oscr)
Memory Breakpoint Occurrence (MBO) Bit 3 The MBO bit is a read-only status bit that is set when debug mode is entered because a memory breakpoint has been encountered. This bit is cleared when leaving debug mode. 10-8 DSP56309UM/D MOTOROLA...
Page 278: Table 10-5 Core Status Bits Description
This significantly increases the programmerÕs ability to monitor what the program is doing in real time. MOTOROLA DSP56309UM/D 10-9...
Page 279: Figure 10-6 Once Memory Breakpoint Logic 0
RAM or ROM and while in any operating mode. Memory accesses are monitored according to the contents of the OBCR as specified in Section 10.5.6ÑOnCE Breakpoint Control Register (OBCR). 10-10 DSP56309UM/D MOTOROLA...
Page 280 JTAG port. Before enabling breakpoints, OMLR1 must be loaded by the external command controller. 10.5.5 OnCE Memory Address Comparator 1 (OMAC1) The OMAC1 compares the current memory address (stored in OMAL0) with the OMLR1 contents. MOTOROLA DSP56309UM/D 10-11...
Page 281: Figure 10-7 Once Breakpoint Control Register (Obcr)
Breakpoint 0 Read/Write Select (RW00ÐRW01) Bits 2Ð3 The RW00ÐRW01 bits define the memory breakpoint 0 to occur when a memory address access is performed for read, write, or both. See Table 10-7 for the definition of the RW00ÐRW01 bits. 10-12 DSP56309UM/D MOTOROLA...
Page 282: Table 10-7 Breakpoint 0 Read/Write Select Table
See Table 10-9 for the definition of the RW10ÐRW11 bits. Table 10-9 Breakpoint 1 Read/Write Select Table RW11 RW10 Description Breakpoint disabled Breakpoint on write access Breakpoint on read access Breakpoint read or write access MOTOROLA DSP56309UM/D 10-13...
Page 283: Table 10-10 Breakpoint 1 Condition Select Table
The OMBC can be read or written through the JTAG port. Every time that the limit register is changed or a different breakpoint event is selected in the OBCR, the breakpoint counter must be written afterwards. This insures that the OnCE 10-14 DSP56309UM/D MOTOROLA...
Page 284: Figure 10-8 Once Trace Logic Block Diagram
To enable trace mode, the counter is loaded with a value, the program counter is set to the start location of the instruction(s) to be executed real time, the TME bit is set in the MOTOROLA DSP56309UM/D 10-15...
Page 285: Methods Of Entering Debug Mode
Holding the DE line asserted during normal chip activity causes the chip to finish the execution of the current instruction and then enter Debug mode. After receiving the acknowledge, the external command controller must negate the DE line before sending 10-16 DSP56309UM/D MOTOROLA...
Page 286 After receiving the acknowledge, the external command controller must negate DE before sending the first command. Note: In this case, the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch. MOTOROLA DSP56309UM/D 10-17...
Page 287: Pipeline Information And Ogdb Register
Figure 10-9 shows the block diagram of the pipeline information registers, with the exception of the PAB registers, which appear in Figure 10-10 on page 10-22. 10-18 DSP56309UM/D MOTOROLA...
Page 288: Figure 10-9 Once Pipeline Information And Gdb Registers
Since there is no direct write access to the instruction latch, the task of restoring is accomplished by writing to OPDBR with no-GO and no-EX. In this case the data written on PDB is transferred into the instruction latch. MOTOROLA DSP56309UM/D 10-19...
Page 289: Debugging Resources
10.9.3 OnCE PAB Register for Execute (OPABEX) The OPABEX is a 16-bit register that stores the address of the instruction currently in the instruction latch. This is the instruction that would have been decoded and executed if 10-20 DSP56309UM/D MOTOROLA...
Page 290 Therefore, it is imperative to read 17 bits of data when reading the 12 trace buffer registers. Since data is read LSB first, the invalid bit is the first bit to be read. MOTOROLA DSP56309UM/D 10-21...
Page 291: Figure 10-10 Once Trace Buffer
To permit an efficient means of communication between the external command controller and the DSP56300 core chip, the following protocol is adopted. Before starting any debugging activity, the external command controller has to wait for an acknowledge 10-22 DSP56309UM/D MOTOROLA...
Page 292: 10.11 Target Site Debug System Requirements
DSP is the only device in the JTAG chain. If there is more than one device in the chain (additional DSPs or other devices), the other devices can be forced to execute the JTAG BYPASS instruction such as their effect in the serial stream will be one bit per additional MOTOROLA DSP56309UM/D 10-23...
Page 293 2. Shift in ENABLE_ONCE. While shifting-in the new instruction, the captured status information is shifted-out. Pass through update-IR. 3. Return to Run-Test/Idle. The external command controller can analyze the information shifted out and detect whether the chip has entered debug mode. 10-24 DSP56309UM/D MOTOROLA...
Page 294 6. Select shift-DR. Shift out the 16 bit OPABEX register. Pass through update-DR. 7. Select shift-DR. Shift in the ÒRead FIFOÓ. Pass through update-DR. 8. Select shift-DR. Shift out the 17 bit FIFO register. Pass through update-DR. 9. Repeat steps 7 and 8 for the entire FIFO (12 times). MOTOROLA DSP56309UM/D 10-25...
Page 295 10.12.6 Displaying X Memory Area Starting at Address $xxxx The DSP56309 must be in debug mode and all actions described in Section 10.12.3ÑSaving Pipeline Information must have been executed. Since R0 is used as pointer for the memory, R0 is saved first. The sequence of actions is as follows: 1.
Page 296 16. Select shift-DR. Shift in the ÒNO SELECT with GO no-EXÓ. Pass through update-DR. This reexecutes the same ÒMOVE X:(R0)+, X:OGDBÓ instruction. 17. Repeat from step 14 to complete the reading of the entire block. When finished, restore the original value of R0. MOTOROLA DSP56309UM/D 10-27...
Page 297 If the device enters debug mode during a DO LOOP, REP instruction, or other Note: special cases such as interrupt processing, STOP, WAIT, or conditional branching, you must first reset the DSP56300 and then proceed with the execution of the new program. 10-28 DSP56309UM/D MOTOROLA...
Page 298: 10.13 Jtag Port/Once Module Interaction
DEBUG_REQUEST (0111) are ..............shifted in while status is shifted out. Shift-IR Idle Exit1-IR Idle Ñ Update-IR Idle The debug request is generated. Select-DR-Scan Idle Ñ Select-IR-Scan Idle Capture-IR Idle The status is sampled in the shifter. MOTOROLA DSP56309UM/D 10-29...
Page 299: Table 10-12 Tms Sequencing For Debug_Request
The four bits of the JTAG ENABLE_ONCE instruction Shift-IR Idle (0110) are shifted into the JTAG instruction register while status is Shift-IR Idle shifted out. Shift-IR Idle Exit1-IR Idle Ñ Update-IR Idle The OnCE module is enabled. 10-30 DSP56309UM/D MOTOROLA...
Page 300: Table 10-13 Tms Sequencing For Enable_Once
The PIL value is loaded in the shifter. Select-DR-Scan Idle Ñ Capture-DR Idle Ñ Shift-DR Idle The 24 bits of the PIL are shifted out (24 steps)..............Shift-DR Idle Exit1-DR Idle Ñ Update-DR Idle Ñ Select-DR-Scan Idle Ñ Capture-DR Idle Ñ MOTOROLA DSP56309UM/D 10-31...
Page 301 This step can be repeated, enabling an external ..........command controller to analyze the information. Run-Test/Idle Idle During Òstep vÓ the external command controller stores the pipeline information. Afterwards, it can proceed with the debug activities as requested by the user. 10-32 DSP56309UM/D MOTOROLA...
Page 302 SECTION 11 JTAG PORT MOTOROLA DSP56309UM/D 11-1...
Page 303 DSP56300 RESTRICTIONS ..... . . 11-12 11.5 DSP56309 BOUNDARY SCAN REGISTER ... 11-13 11-2...
Page 304: Introduction
DSP56300 core implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document. Figure 11-1 shows a block diagram of the TAP port. MOTOROLA DSP56309UM/D 11-3...
Page 305: Figure 11-1 Tap Block Diagram
Figure 11-1 TAP Block Diagram 11.2 JTAG SIGNALS As described in the IEEE 1149.1 document, the JTAG port requires a minimum of four signals to support TDI, TDO, TCK, and TMS signals. The DSP56300 family also provides 11-4 DSP56309UM/D MOTOROLA...
Page 306 JTAG Port JTAG Signals the optional TRST signal. On the DSP56309, the debug event (DE) signal is provided for use by the OnCE module; it is documented in Section 10ÑOn-Chip Emulation Module. The signal functions are described in the following paragraphs.
Page 307: Figure 11-2 Tap Controller State Machine
TMS signal sampled on the rising edge of TCK signal. For a description of the TAP controller states, refer to the IEEE 1149.1 document. Test-Logic-Reset Select-IR-Scan Run-Test/Idle Select-DR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-IR Pause-DR Exit2-DR Exit2-IR Update-DR Update-IR AA0114 Figure 11-2 TAP Controller State Machine 11-6 DSP56309UM/D MOTOROLA...
Page 308: Figure 11-3 Jtag Instruction Register
11.3.1 Boundary Scan Register (BSR) The BSR in the DSP56309 JTAG implementation contains bits for all device signal and clock signals and associated control signals. All DSP56309 bidirectional signals have a single register bit in the BSR for signal data; each such signal is controlled by an associated control bit in the BSR.
Page 309: Table 11-1 Jtag Instructions
DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations. By using the TAP, the BSR is capable of the following: ¥ Scanning user-defined values into the output buffers ¥ Capturing values presented to input signals 11-8 DSP56309UM/D MOTOROLA...
Page 310: Figure 11-4 Jtag Id Register
As more components emerge which conform to the IEEE 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to blindly interrogate a board design in order to determine the type of each component in MOTOROLA DSP56309UM/D 11-9...
Page 311 MotorolaÕs manufacturer identity is 00000001110. The customer part number consists of two parts: Motorola design center number (bits 27:22) and a sequence number (bits 21:12). The sequence number is divided into two parts: core number (bits 21:17) and chip derivative number (bits 16:12).
Page 312: Figure 11-5 Bypass Register
0 on the rising edge of TCK in the Capture-DR controller state. Therefore, the first bit shifted out after selecting the bypass register is always a logical 0. Shift DR To TDO From TDI AA0115 CLOCKDR Figure 11-5 Bypass Register MOTOROLA DSP56309UM/D 11-11...
Page 313: Dsp56300 Restrictions
V achieve minimal power consumption. Since during stop mode all DSP56309 core clocks are disabled, the JTAG interface provides the means of polling the device status (sampled in the Capture-IR state).
Page 314: Table 11-2 Dsp56309 Bsr Bit Definitions
JTAG Port DSP56309 Boundary Scan Register 11.5 DSP56309 BOUNDARY SCAN REGISTER Table 11-2 provides a listing of the contents of the BSR for the DSP56309. Table 11-2 DSP56309 BSR Bit Definitions Bit # Cell Type Signal Name Signal Type BSR Cell Type...
Page 315 JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # Cell Type Signal Name Signal Type BSR Cell Type BC_6 Input/Output Data BC_6 Input/Output Data BC_6 Input/Output Data BC_6 Input/Output Data BC_1 D[11:0] Ñ Control...
Page 316 JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # Cell Type Signal Name Signal Type BSR Cell Type BC_2 Output Data BC_2 Output Data BC_2 Output Data BC_2 Output Data BC_2 CLKOUT Output Data...
Page 317 JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # Cell Type Signal Name Signal Type BSR Cell Type BC_6 HAS/A0 Input/Output Data BC_1 HA8/A1 Ñ Control BC_6 HA8/A1 Input/Output Data BC_1 HA9/A2 Ñ Control...
Page 318 JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # Cell Type Signal Name Signal Type BSR Cell Type BC_6 SCK1 Input/Output Data BC_1 GPIO2 Ñ Control BC_6 GPIO2 Input/Output Data BC_1 GPIO1 Ñ Control...
Page 319 JTAG Port DSP56309 Boundary Scan Register Table 11-2 DSP56309 BSR Bit Definitions (Continued) Bit # Cell Type Signal Name Signal Type BSR Cell Type BC_6 STD1 Input/Output Data BC_1 SRD1 Ñ Control BC_6 SRD1 Input/Output Data BC_1 SC11 Ñ Control...
Page 320 ; EPROM, from the Host Interface or from the SCI serial interface. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1000, then the Boot ROM is bypassed and the DSP56309 will ; If MD:MC:MB:MA=1000, then the Boot ROM is bypassed and the DSP56302 will ; start fetching instructions beginning with the address $8000 assuming ;...
Page 321 ; Revised March, 18 1997. ; Bootstrap through the Host Interface, External EPROM or SCI. ; This is the Bootstrap program contained in the DSP56309 192-word Boot ; ROM. This program can load any program RAM segment from an external ;...
Page 322 ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by setting the ; Host Flag 0 (HF0). This will start execution of the loaded program from MOTOROLA DSP56309UM/D...
Page 323 $1c00 endif start_pram ;; 20k PRAM length_pram $5000 ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; BOOT $D00000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM would be located DSP56309UM/D MOTOROLA...
Page 324 ; When the downloading is terminated, the program will start execution of the ; loaded program from the specified starting address. ; The HI08 boot ROM program enables the following busses to download programs ; through the HI08 port: MOTOROLA DSP56309UM/D...
Page 325 ; HASP = 0 (address strobe polarity has no meaning in non-multiplexed bus) ; HDSP = 0 Negative data stobes polarity ; HROD = 0 Host request is active when enabled ; spare = 0 This bit should be set to 0 for future compatability DSP56309UM/D MOTOROLA...
Page 326 ; spare = 0 This bit should be set to 0 for future compatability ; HEN = 0 When the HPCR register is modified HEN should be cleared ; HAEN = 0 Host acknowledge is disabled ; HREN = 1 Host requests are enabled MOTOROLA DSP56309UM/D...
Page 327 ; Wait for RDRF to go high movep X:M_SRXL,A2 ; Put 8 bits in A2 jclr #1,X:M_SSR,* ; Wait for TDRE to go high movep A2,X:M_STXL ; echo the received byte asr #8,a,a _LOOP6 move a1,r0 ; starting address for load DSP56309UM/D MOTOROLA...
Page 328 ; expanded mode and jumps to the RESET vector. andi #$0,ccr ; Clear CCR as if RESET to 0. jmp (r1) ; Then go to starting Prog addr. ;======================================================================== ; The following modes are reserved, some of which are used for internal testing MOTOROLA DSP56309UM/D...
Page 329 ;; write pattern to all memory locations (EQUALDATA) ;; x/y ram symmetrical ;; write x and y memory clr a #start_dram,r0 ;; start of x/y ram move #>length_dram,n0 ;; length of x/y ram mac x0,x1,a x,l:(r0)+ ;; exercise mac, write x/y ram A-10 DSP56309UM/D MOTOROLA...
Page 330 ;; restore pointer, clear a n0,_loopx move x:(r0)+,a1 ;; a0=a2=0 x1,a ;; accumulate error in b _loopx ;; check yram clr a #start_yram,r1 ;; restore pointer, clear a n1,_loopy move y:(r1)+,a1 ;; a0=a2=0 x0,a ;; accumulate error in b MOTOROLA DSP56309UM/D A-11...
Page 331 ;; toggle pin and keep on looping burn1 wait ;; enter wait after test completion ORG PL:,PL: PATTERNS ;; align for correct modulo addressing PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories $555555 $AAAAAA $333333 $F0F0F0 NUM_PATTERNS *-PATTERNS A-12 DSP56309UM/D MOTOROLA...
Page 332 APPENDIX B EQUATES ;***************************************************************************** ;***************************************************************************** EQUATES for DSP56309 I/O registers and ports EQUATES for 56302 I/O registers and ports Last update: March 1998 Last update: June 11 1995 ;***************************************************************************** ;***************************************************************************** page 132,55,0,0,0 page 132,55,0,0,0 ioequ ident ioequ ident ;------------------------------------------------------------------------ ;------------------------------------------------------------------------...
Page 333 BUS INTERFACE UNIT (BIU) EQUATES ....B-13 B.10 INTERRUPT EQUATES ......B-15 DSP56309UM/D MOTOROLA...
Page 334 ; Host Transmit Interrupt Enable M_HCIE ; Host Command Interrupt Enable M_HF2 ; Host Flag 2 M_HF3 ; Host Flag 3 HSR bits definition M_HRDF ; Host Receive Data Full M_HTDE ; Host Receive Data Empty M_HCP ; Host Command Pending MOTOROLA DSP56309UM/D...
Page 335 SCI Control Register Bit Flags M_WDS ; Word Select Mask (WDS0-WDS3) M_WDS0 ; Word Select 0 M_WDS1 ; Word Select 1 M_WDS2 ; Word Select 2 M_SSFTD EQU ; SCI Shift Direction M_SBK ; Send Break M_WAKE ; Wakeup Mode Select DSP56309UM/D MOTOROLA...
Page 336 ; SSI0 Status Register M_CRB0 $FFFFB6 ; SSI0 Control Register B M_CRA0 $FFFFB5 ; SSI0 Control Register A M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B MOTOROLA DSP56309UM/D...
Page 337 ; SSI Transmit #2 Enable M_SSTE1 EQU ; SSI Transmit #1 Enable M_SSTE0 EQU ; SSI Transmit #0 Enable M_SSRE ; SSI Receive Enable M_SSTIE EQU ; SSI Transmit Interrupt Enable M_SSRIE EQU ; SSI Receive Interrupt Enable DSP56309UM/D MOTOROLA...
Page 338 ; Interrupt Priority Register Peripheral Interrupt Priority Register Core (IPRC) M_IAL ; IRQA Mode Mask M_IAL0 ; IRQA Mode Interrupt Priority Level (low) M_IAL1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 ; IRQA Mode Trigger Mode M_IBL ; IRQB Mode Mask MOTOROLA DSP56309UM/D...
Page 339 ; SCI Interrupt Priority Level Mask M_SCL0 ; SCI Interrupt Priority Level (low) M_SCL1 ; SCI Interrupt Priority Level (high) M_T0L $300 ; TIMER Interrupt Priority Level Mask M_T0L0 ; TIMER Interrupt Priority Level (low) M_T0L1 ; TIMER Interrupt Priority Level (high) DSP56309UM/D MOTOROLA...
Page 340 ; Data Input M_DO ; Data Output M_PCE ; Prescaled Clock Enable M_TOF ; Timer Overflow Flag M_TCF ; Timer Compare Flag Timer Prescaler Register Bit Flags M_PS $600000 ; Prescaler Source Mask M_PS0 M_PS1 Timer Control Bits MOTOROLA DSP56309UM/D...
Page 341 ; DMA2 Control Register Register Addresses Of DMA4 M_DSR3 $FFFFE3 ; DMA3 Source Address Register M_DDR3 $FFFFE2 ; DMA3 Destination Address Register M_DCO3 $FFFFE1 ; DMA3 Counter M_DCR3 $FFFFE0 ; DMA3 Control Register Register Addresses Of DMA4 B-10 DSP56309UM/D MOTOROLA...
Page 342 $380000 ; DMA Transfer Mode Mask ;(DTM2-DTM0) M_DTM0 ; DMA Transfer Mode 0 M_DTM1 ; DMA Transfer Mode 1 M_DTM2 ; DMA Transfer Mode 2 M_DIE ; DMA Interrupt Enable bit M_DE ; DMA Channel Enable bit MOTOROLA DSP56309UM/D B-11...
Page 343 M_XTLR ; XTAL Range select bit M_XTLD ; XTAL Disable Bit M_PSTP ; STOP Processing State Bit M_PEN ; PLL Enable Bit M_PCOD ; PLL Clock Output Disable Bit M_PD $F00000 ; PreDivider Factor Bit Mask (PD0-PD3) B-12 DSP56309UM/D MOTOROLA...
Page 344 ; External Access Type and Pin Definition Bits Mask BAT(1:0) M_BAAP ; Address Attribute Pin Polarity M_BPEN ; Program Space Enable M_BXEN ; X Data Space Enable M_BYEN ; Y Data Space Enable M_BAM ; Address Muxing M_BPAC ; Packing Enable MOTOROLA DSP56309UM/D B-13...
Page 345 ; Stack Extension space select bit in OMR. M_EUN ; Extended stack UNderflow flag in OMR. M_EOV ; Extended stack OVerflow flag in OMR. M_WRP ; Extended WRaP flag in OMR. M_SEN ; Stack Extension Enable bit in OMR. B-14 DSP56309UM/D MOTOROLA...
Page 346 Equates B.10 INTERRUPT EQUATES ;*************************************************************** EQUATES for DSP56309 interrupts ;************************************************************** ;--------------------------------------------------------------- ; Non-Maskable interrupts ;--------------------------------------------------------------- I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ;...
Page 347 ;--------------------------------------------------------------- I_HRDF I_VEC+$60 ; Host Receive Data Full I_HTDE I_VEC+$62 ; Host Transmit Data Empty I_HC I_VEC+$64 ; Default Host Command ;--------------------------------------------------------------- ; INTERRUPT ENDING ADDRESS ;--------------------------------------------------------------- I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space B-16 DSP56309UM/D MOTOROLA...
Page 348 APPENDIX C DSP56309 BSDL LISTING -- M O T O R O L A S S D T J T A G S O F T W A R E -- M O T O R O L A S S D T...
Page 349 DSP56309 BSDL Listing -- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Tue Mar 3 15:14:41 1998 -- Revision History: entity DSP56309 is generic (PHYSICAL_PIN_MAP : string := ÒTQFP144Ó);...
Page 350 HA9:inout bit; HA8:inout bit; HAS:inout bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56309 : entity is ÒSTD_1149_1_1993Ó; attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP; constant TQFP144 : PIN_MAP_STRING := ÒSRD1: 1, Ò & ÒSTD1: 2, Ò & ÒSC02: 3, Ò &...
Page 351 DSP56309 BSDL Listing ÒQGND: (19, 54, 90, 127), Ò & ÒRESERVED: (49, 20), Ò & ÒHDS: 21, Ò & ÒHRW: 22, Ò & ÒHACK: 23, Ò & ÒHREQ: 24, Ò & ÒTIO2: 27, Ò & ÒTIO1: 28, Ò & ÒTIO0: 29, Ò...
Page 352 TMS : signal is true; attribute TAP_SCAN_RESET of TRST_N : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56309 : entity is ÒEXTEST (0000),Ó &...
Page 353 DSP56309 BSDL Listing Ò17 (BC_6, D(11), bidir, Z),Ó & Ò18 (BC_6, D(10), bidir, Z),Ó & Ò19 (BC_6, D(9), bidir, Z),Ó & -- num cell port func safe [ccell dis rslt] Ò20 (BC_6, D(8), bidir, Z),Ó & Ò21 (BC_6, D(7), bidir, Z),Ó...
Page 354 DSP56309 BSDL Listing Ò67 (BC_1, *, control, 1),Ó & Ò68 (BC_1, EXTAL, input, X),Ó & Ò69 (BC_1, CAS_N, output3, Z),Ó & Ò70 (BC_1, AA(2), output3, Z),Ó & Ò71 (BC_1, AA(3), output3, Z),Ó & Ò72 (BC_1, RESET_N, input, X),Ó & Ò73...
Page 355 -- Revision History: -- 1) Date : Tue Mar 3 15:14:41 1998 Changes : Created for dsp56309 rev0, PBGA -- 2) Date : Wed May 20 10:37:28 1998 Changes : Fix in definition of DE_N, it is Pull1 when disabled...
Page 356 DSP56309 BSDL Listing STD0: inout bit; SCK0: inout bit; SRD0: inout bit; SRD1: inout bit; SCK1: inout bit; STD1: inout bit; SC10: inout bit; SC11: inout bit; SC12: inout bit; TXD: inout bit; SCLK: inout bit; RXD: inout bit; TIO0: inout bit;...
Page 357 HA8: inout bit; HAS: inout bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56309 : entity is ÒSTD_1149_1_1993Ó; attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP; constant TQFP144 : PIN_MAP_STRING := ÒSRD1: 1, Ò & ÒSTD1: 2, Ò & ÒSC02: 3, Ò &...
Page 358 TMS : signal is true; attribute TAP_SCAN_RESET of TRST_N : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56309 : entity is MOTOROLA DSP56309UM/D C-11...
Page 359 ÒHIGHZ (0100),Ó & ÒENABLE_ONCE (0110),Ó & ÒDEBUG_REQUEST (0111),Ó & ÒBYPASS (1111)Ó; attribute INSTRUCTION_CAPTURE of DSP56309 : entity is Ò0001Ó; attribute IDCODE_REGISTER of DSP56309 : entity is Ò0010Ó & -- version Ò000110Ó & -- manufacturerÕs use Ò0000000010Ó & -- sequence number Ò00000001110Ó...
Page 360 DSP56309 BSDL Listing Ò28 (BC_6, D(1), bidir, Z),Ó & Ò29 (BC_6, D(0), bidir, Z),Ó & Ò30 (BC_1, A(17), output3, Z),Ó & Ò31 (BC_1, A(16), output3, Z),Ó & Ò32 (BC_1, A(15), output3, Z),Ó & Ò33 (BC_1, *, control, 1),Ó & Ò34...
Page 361 DSP56309 BSDL Listing Ò79 (BC_1, *, control, 1),Ó & -- num cell port func safe [ccell dis rslt] Ò80 (BC_6, HAD(3), bidir, Z),Ó & Ò81 (BC_1, *, control, 1),Ó & Ò82 (BC_6, HAD(4), bidir, Z),Ó & Ò83 (BC_1, *, control, 1),Ó...
Page 362 DSP56309 BSDL Listing Ò129 (BC_1, PINIT, input, X),Ó & Ò130 (BC_1, *, control, 1),Ó & Ò131 (BC_6, DE_N, bidir, 130, Pull1),Ó & Ò132 (BC_1, *, control, 1),Ó & Ò133 (BC_6, SC01, bidir, 132, Z),Ó & Ò134 (BC_1, *, control, 1),Ó &...
Page 363 PGND: linkage bit; PGND1: linkage bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56309 : entity is ÒSTD_1149_1_1993Ó; attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP; constant PBGA196 : PIN_MAP_STRING := ÒRESERVED: (A1, A14, B14, P1, P14), Ò & ÒSC11: A2, Ò &...
Page 364 DSP56309 BSDL Listing ÒTMS: A3, Ò & ÒTDO: A4, Ò & ÒMODB: A5, Ò & ÒD: (E14, D12, D13, C13, C14, B13, C12, A13, B12, A12, B11, A11, C10, B10, A10, B9, Ò & ÒA9, B8, C8, A8, B7, B6, C6, A6), Ò &...
Page 365 TMS : signal is true; attribute TAP_SCAN_RESET of TRST_N : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56309 : entity is ÒEXTEST (0000),Ó &...
Page 366 DSP56309 BSDL Listing attribute BOUNDARY_REGISTER of DSP56309 : entity is -- num cell port func safe [ccell dis rslt] Ò0 (BC_1, MODA, input, X),Ó & Ò1 (BC_1, MODB, input, X),Ó & Ò2 (BC_1, MODC, input, X),Ó & Ò3 (BC_1, MODD, input, X),Ó...
Page 367 DSP56309 BSDL Listing Ò48 (BC_1, A(1), output3, Z),Ó & Ò49 (BC_1, A(0), output3, Z),Ó & Ò50 (BC_1, BG_N, input, X),Ó & Ò51 (BC_1, AA(0), output3, Z),Ó & Ò52 (BC_1, AA(1), output3, Z),Ó & Ò53 (BC_1, RD_N, output3, Z),Ó & Ò54...
Page 368 DSP56309 BSDL Listing Ò99 (BC_1, *, control, 1),Ó & -- num cell port func safe [ccell dis rslt] Ò100 (BC_6, TIO1, bidir, Z),Ó & Ò101 (BC_1, *, control, 1),Ó & Ò102 (BC_6, TIO2, bidir, 101, Z),Ó & Ò103 (BC_1, *, control, 1),Ó...
Page 369 DSP56309 BSDL Listing C-22 DSP56309UM/D MOTOROLA...
Page 370 APPENDIX D PROGRAMMING REFERENCE MOTOROLA DSP56309UM/D...
Page 371 TIMERS ........D-33 GENERAL PURPOSE I/O (GPIO)....D-36 DSP56309UM/D MOTOROLA...
Page 372 Table D-2 on page -11 lists the interrupt starting addresses and sources. D.1.3 Interrupt Priorities Table D-3 on page -13 lists the priorities of specific interrupts within interrupt priority levels. D.1.4 Programming Sheets The remaining figures show the major programmable registers on the DSP56309. MOTOROLA DSP56309UM/D...
Page 373: Table D-1 Internal I/O Memory Map
DMA Offset Register 2 (DOR2) $FFF0 $FFFFF0 DMA Offset Register 3 (DOR3) DMA0 $FFEF $FFFFEF DMA Source Address Register (DSR0) $FFEE $FFFFEE DMA Destination Address Register (DDR0) $FFED $FFFFED DMA Counter (DCO0) $FFEC $FFFFEC DMA Control Register (DCR0) DSP56309UM/D MOTOROLA...
Page 374 DMA Destination Address Register (DDR4) $FFDD $FFFFDD DMA Counter (DCO4) $FFDC $FFFFDC DMA Control Register (DCR4) DMA5 $FFDB $FFFFDB DMA Source Address Register (DSR5) $FFDA $FFFFDA DMA Destination Address Register (DDR5) $FFD9 $FFFFD9 DMA Counter (DCO5) $FFD8 $FFFFD8 DMA Control Register (DCR5) MOTOROLA DSP56309UM/D...
Page 375 $FFC6 $FFFFC6 Host Receive Register (HRX) $FFC5 $FFFFC5 Host Base Address Register (HBAR) $FFC4 $FFFFC4 Host Polarity Control Register (HPCR) $FFC3 $FFFFC3 Host Status Register (HSR) $FFC2 $FFFFC2 Host Control Register (HCR) $FFC1 $FFFFC1 Reserved $FFC0 $FFFFC0 Reserved DSP56309UM/D MOTOROLA...
Page 376 $FFB1 $FFFFB1 ESSI 0 Receive Slot Mask Register B (RSMB0) Ñ $FFB0 $FFFFB0 Reserved PORT D $FFAF $FFFFAF Port D Control Register (PCRD) $FFAE $FFFFAE Port D Direction Register (PRRD) $FFAD $FFFFAD Port C GPIO Data Register (PDRD) MOTOROLA DSP56309UM/D...
Page 377 $FFA1 $FFFFA1 ESSI 1 Receive Slot Mask Register B (RSMB1) Ñ $FFA0 $FFFFA0 Reserved PORT E $FF9F $FFFF9F Port E Control Register (PCRE) $FF9E $FFFF9E Port E Direction Register (PRRE) $FF9D $FFFF9D Port E GPIO Data Register (PDRE) DSP56309UM/D MOTOROLA...
Page 378 SCI Transmit Data Register - Middle (STXM) $FF95 $FFFF95 SCI Transmit Data Register - Low (STXL) $FF94 $FFFF94 SCI Transmit Address Register (STXA) $FF93 $FFFF93 SCI Status Register (SSR) Ñ $FF92 $FFFF92 Reserved $FF91 $FFFF91 Reserved $FF90 $FFFF90 Reserved MOTOROLA DSP56309UM/D...
Page 379 Timer 2 Load Register (TLR2) $FF85 $FFFF85 Timer 2 Compare Register (TCPR2) $FF84 $FFFF84 Timer 2 Count Register (TCR2) $FF83 $FFFF83 Timer Prescaler Load Register (TPLR) $FF82 $FFFF82 Timer Prescaler Count Register (TPCR) Ñ $FF81 $FFFF81 Reserved $FF80 $FFFF80 Reserved D-10 DSP56309UM/D MOTOROLA...
Page 380: Table D-2 Interrupt Sources
TIMER 1 Overflow VBA:$2C 0Ð2 TIMER 2 Compare VBA:$2E 0Ð2 TIMER 2 Overflow VBA:$30 0Ð2 ESSI0 Receive Data VBA:$32 0Ð2 ESSI0 Receive Data With Exception Status VBA:$34 0Ð2 ESSI0 Receive Last Slot VBA:$36 0Ð2 ESSI0 Transmit Data MOTOROLA DSP56309UM/D D-11...
Page 381 SCI Idle Line VBA:$58 0Ð2 SCI Timer VBA:$5A 0Ð2 Reserved VBA:$5C 0Ð2 Reserved VBA:$5E 0Ð2 Reserved VBA:$60 0Ð2 Host Receive Data Full VBA:$62 0Ð2 Host Transmit Data Empty VBA:$64 0Ð2 Host Command (Default) VBA:$66 0Ð2 Reserved VBA:$FE 0Ð2 Reserved D-12 DSP56309UM/D MOTOROLA...
Page 382: Table D-3 Interrupt Source Priorities Within An Ipl
DMA Channel 2 Interrupt Ñ DMA Channel 3 Interrupt Ñ DMA Channel 4 Interrupt Ñ DMA Channel 5 Interrupt Ñ Host Command Interrupt Ñ Host Transmit Data Empty Ñ Host Receive Data Full Ñ ESSI0 RX Data with Exception Interrupt MOTOROLA DSP56309UM/D D-13...
Page 383 SCI Receive Data Ñ SCI Transmit Data Ñ SCI Idle Line Ñ SCI Timer Ñ TIMER0 Overflow Interrupt Ñ TIMER0 Compare Interrupt Ñ TIMER1 Overflow Interrupt Ñ TIMER1 Compare Interrupt Ñ TIMER2 Overflow Interrupt Lowest TIMER2 Compare Interrupt D-14 DSP56309UM/D MOTOROLA...
Page 384: Figure D-1 Status Register (Sr
19 18 17 16 15 14 13 12 11 10 9 Extended Mode Register (MR) Mode Register (MR) Condition Code Register (CCR) Status Register (SR) = Reserved, Program as 0 Read/Write Reset = $C00300 Figure D-1 Status Register (SR) MOTOROLA DSP56309UM/D D-15...
Page 385: Figure D-2 Operating Mode Register (Omr
Chip Operating Mode Status Register (SCS) Mode Register (COM) Register (COM) Operating Mode Register (OMR) = Reserved, Program as 0 Read/Write X = Latched from levels on Mode pins Reset = $00030X Figure D-2 Operating Mode Register (OMR) D-16 DSP56309UM/D MOTOROLA...
Page 386: Figure D-3 Interrupt Priority Registerðcore (Iprðc
Programming Reference Date: Application: Programmer: Sheet 3 of 5 Figure D-3 Interrupt Priority RegisterÐCore (IPRÐC) MOTOROLA DSP56309UM/D D-17...
Page 387: Figure D-4 Interrupt Priority Register Ð Peripherals (Iprðp
Programming Reference Date: Application: Programmer: Sheet 4 of 5 Figure D-4 Interrupt Priority Register Ð Peripherals (IPRÐP) D-18 DSP56309UM/D MOTOROLA...
Page 388: Figure D-5 Phase-Locked Loop Control Register (Pctl
Programming Reference Date: Application: Programmer: Sheet 5 of 5 Figure D-5 Phase-Locked Loop Control Register (PCTL) MOTOROLA DSP56309UM/D D-19...
Page 389: Figure D-6 Host Receive And Host Transmit Data Registers
19 18 17 16 15 14 13 12 11 10 9 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Data Register (HTX) X:$FFEC7 Write Only Reset = empty Figure D-6 Host Receive and Host Transmit Data Registers D-20 DSP56309UM/D MOTOROLA...
Page 390: Figure D-7 Host Control And Host Status Registers
0 = ¸ Wait 1 = ¸ Ready Host Flags Read Only HTDE HRDF Host Staus Register (HSR) X:$FFFFC3 Read Only Reset = $2 = Reserved, Program as 0 Figure D-7 Host Control and Host Status Registers MOTOROLA DSP56309UM/D D-21...
Page 391: Figure D-8 Host Base Address And Host Port Control Registers
HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN HA8EN HGEN Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $0 = Reserved, Program as 0 Figure D-8 Host Base Address and Host Port Control Registers D-22 DSP56309UM/D MOTOROLA...
Page 392: Figure D-9 Interrupt Control And Interrupt Status Registers
Host Request 0 = ¸ HREQ Deasserted 1 = ¸ HREQ Asserted HREQ TRDY TXDE RXDF Interrupt Status Register (ISR) $2 Read/Write Reset = $06 = Reserved, Program as 0 Figure D-9 Interrupt Control and Interrupt Status Registers MOTOROLA DSP56309UM/D D-23...
Page 393: Figure D-10 Interrupt Vector And Command Vector Registers
Host Vector Contains Host Command Interrupt Address Ö 2 Host Command Handshakes Executing Host Command Interrupts Command Vector Register (CVR) Reset = $2A Contains the host command interrupt address Figure D-10 Interrupt Vector and Command Vector Registers D-24 DSP56309UM/D MOTOROLA...
Page 394: Figure D-11 Host Receive And Host Transmit Data Registers
Host Transmit Data (usually loaded by program) Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = $00 Figure D-11 Host Receive and Host Transmit Data Registers MOTOROLA DSP56309UM/D D-25...
Page 395: Figure D-12 Essi Control Register A (Cra
Programming Reference Date: Application: Programmer: Sheet 1 of 4 Figure D-12 ESSI Control Register A (CRA) D-26 DSP56309UM/D MOTOROLA...
Page 396: Figure D-13 Essi Control Register B (Crb
Programming Reference Date: Application: Programmer: Sheet 2 of 4 Figure D-13 ESSI Control Register B (CRB) MOTOROLA DSP56309UM/D D-27...
Page 397: Figure D-14 Essi Status Register (Ssisr
1 = ¸ Write Receive Data Register Full 0 = ¸ Wait 1 = ¸ Read SSI Status Register (SSISRx) ESSI0: $FFFFB7 (Read) ESSI1: $FFFFA7 (Read) SSI Status Bits = Reserved, program as 0 Figure D-14 ESSI Status Register (SSISR) D-28 DSP56309UM/D MOTOROLA...
Page 398: Figure D-15 Essr Transmit And Receive Slot Mask Registers (Tsm, Rsm
RS21 RS20 RS19 RS18 RS17 RS16 RSMBx ESSI0: $FFFFB1 Read/Write ESSI1: $FFFFA1 Read/Write Reset = $FFFF ESSI Receive Slot Mask B = Reserved, Program as 0 Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM) MOTOROLA DSP56309UM/D D-29...
Page 399: Figure D-16 Sci Control Register (Scr
15 14 13 12 11 10 9 SCI Control REIE SCKP STIR TMIE ILIE WOMS WAKE SBK SSFTD WDS2 WDS1 WDS0 Register (SCR) Address X:$FFFF9C Read/Write = Reserved, Program as 0 SCI Control Register (SCR) Figure D-16 SCI Control Register (SCR) D-30 DSP56309UM/D MOTOROLA...
Page 400: Figure D-17 Sci Status And Clock Control Registers (Ssr, Sccr
0 = Ö1 1 = Ö 8 15 14 13 12 11 10 TCM RCM COD CD11 CD10 CD9 = Reserved, Program as 0 SCI Clock Control Register (SCCR) Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR) MOTOROLA DSP56309UM/D D-31...
Page 401: Figure D-18 Sci Receive And Transmit Data Registers (Srx, Trx
Address X:$FFFF98 Ð X:$FFFF9A X:$FFFF99 Read Reset = xxxxxx X:$FFFF98 Packing ÒAÓ ÒBÓ ÒCÓ Note: STX is the same register decoded at three different addresses SCI Receive Data Registers Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX) D-32 DSP56309UM/D MOTOROLA...
Page 402: Figure D-19 Timer Prescaler Load/Count Register (Tplr, Tpcr
15 14 13 12 11 10 9 Current Value of Prescaler Counter (PC [0:20]) Timer Prescaler Count Register = Reserved, Program as 0 TPCR:$FFFF82 Read Only Reset = $000000 Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR) MOTOROLA DSP56309UM/D D-33...
Page 403: Figure D-20 Timer Control/Status Register (Tcsr
19 18 17 16 15 14 13 12 11 10 9 TRM INV TCIE TQIE Timer Control/Status Register = Reserved, Program as 0 TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset = $000000 Figure D-20 Timer Control/Status Register (TCSR) D-34 DSP56309UM/D MOTOROLA...
Page 404: Figure D-21 Timer Load, Compare, Count Registers (Tlr, Tcpr, Tcr
19 18 17 16 15 14 13 12 11 10 9 Timer Count Value Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset = $000000 Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR) MOTOROLA DSP56309UM/D D-35...
Page 406: Figure D-23 Port C Registers (Pcrc, Prrc, Pdrc
GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n = Reserved, Program as 0 Figure D-23 Port C Registers (PCRC, PRRC, PDRC) MOTOROLA DSP56309UM/D D-37...
Page 407: Figure D-24 Port D Registers (Pcrd, Prrd, Pdrd
GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n = Reserved, Program as 0 Figure D-24 Port D Registers (PCRD, PRRD, PDRD) D-38 DSP56309UM/D MOTOROLA...
Page 408 GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n = Reserved, Program as 0 Figure D-25 Port E Registers (PCRE, PRRE, PDRE) MOTOROLA DSP56309UM/D D-39...
Page 410 COD bit 8-16 Breakpoint 0 Condition Code Select bits code (CC00ÐCC01) 10-13 compatible 1-7 Breakpoint 0 Read/Write Select bits column address strobe signal (CAS) 2-13 (RW00ÐRW01) 10-12 CRA register 7-11 Breakpoint 1 Condition Code Select bits (CC10ÐCC11) 10-14 MOTOROLA DSP56309UM/D...
Page 411 20ÑESSI Transmit Last Slot Interrupt (ESSI) 1-16 2-25 2-28 Enable bit (TLIE) 7-26 Enhanced Synchronous Serial Interface 0 2-24 bit 21ÑESSI Receive Last Slot Interrupt Enable Enhanced Synchronous Serial Interface 1 2-28 bit (RLIE) 7-27 equates BIU B-13 DSP56309UM/D MOTOROLA...
Page 412 ESSI Status Register (SSISR) 7-27 ESSI Time Slot Register (TSR) 7-34 ESSI Transmit 0 Enable bit (TE0) 7-24 general purpose input/output (GPIO) 2-34 ESSI Transmit 1 Enable bit (TE1) 7-23 Global Data Bus 1-13 ESSI Transmit 2 Enable bit (TE2) 7-22 MOTOROLA DSP56309UM/D...
Page 413 Host Receive Data Register (HRX) 6-8 HCR register 6-9 6-10 host side bit 0ÑHost Receive Interrupt Enable bit Interface Control Register (ICR) 6-22 (HRIE) 6-10 Interface Status Register (ISR) 6-26 bit 1ÑHost Transmit Interrupt Enable bit Interface Vector Register (IVR) 6-28 (HTIE) 6-10 DSP56309UM/D MOTOROLA...
Page 414 12ÑHost Dual Data Strobe bit (HDDS) 6-15 Host Flag 0 bit (HF0) 6-24 bit 13ÑHost Chip Select Polarity bit Host Flag 1 bit (HF1) 6-24 (HCSP) 6-16 Host Flag 2 and 3 bits (HF2, HF3) 6-10 bit 14ÑHost Request Polarity bit (HRP) 6-16 MOTOROLA DSP56309UM/D...
Page 415 Idle Line Interrupt Enable bit (ILIE) 8-11 Joint Test Action Group (JTAG) 11-3 IF0 bit 7-28 JTAG 1-11 2-35 IF1 bit 7-28 JTAG instructions ILIE bit 8-11 BYPASS instruction 11-11 IME bit 10-8 CLAMP instruction 11-10 instruction cache 3-3 DEBUG_REQUEST instruction 11-11 DSP56309UM/D MOTOROLA...
Page 416 OMLR1 register 10-11 MODA/IRQA 2-14 OMR register 1-11 MODB/IRQB 2-15 OnCE 1-4 MODC/IRQC 2-15 commands 10-23 MODD/IRQD 2-16 controller 10-4 mode control 2-14 2-15 trace logic 10-15 Mode Select bit (MOD) 7-20 OnCE Breakpoint Control Register (OBCR) 10-12 MOTOROLA DSP56309UM/D...
Page 417 X data RAM 3-6 PC0-PC20 bits 9-9 Y data RAM 3-7 PC1 signal 2-25 OPABDR register 10-20 PC2 signal 2-25 OPABEX register 10-20 PC3 signal 2-26 OPABFR register 10-20 PC4 signal 2-26 OPDBR register 10-19 PC5 signal 2-27 Operating 4-3 DSP56309UM/D MOTOROLA...
Page 418 B 9 signal (PB9) 2-19 Program Address Bus (PAB) 1-13 port B signal (PB0ÐPB7) 2-18 Program Address Generator (PAG) 1-10 Port C 2-3 2-24 2-25 2-28 Program Control Unit (PCU) 1-10 port C 0 signal (PC0) 2-24 Program Counter register (PC) 1-10 MOTOROLA DSP56309UM/D...
Page 419 REIE bit 7-27 8-13 SBK bit 8-9 reserved bits SC register 1-11 in CRA register 7-11 7-13 7-14 SC0 signal 7-6 in HBAR register SC00 signal 2-24 bits 5Ð15 6-12 SC01 signal 2-25 in HCR register SC02 signal 2-25 I-10 DSP56309UM/D MOTOROLA...
Page 420 2 signal (SC12) 2-29 SCI Status Register (SSR) 8-13 Serial Input Flag 0 bit (IF0) 7-28 SCI Transmit Register (STX) Serial Input Flag 1 bit (IF1) 7-28 STX register 8-20 Serial Output Flag bits (OF0ÐOF1) 7-15 MOTOROLA DSP56309UM/D I-11...
Page 421 7ÑReceive Data Register Full bit TDE bit 7-29 (RDF) 7-30 TDI pin 11-5 SSR register 8-13 TDI signal 2-35 bit 1ÑTransmitter Empty bit (TRNE) 8-13 TDO signal 2-36 bit 2ÑReceive Data Register Full bit TDRE bit 8-13 (RDRF) 8-14 I-12 DSP56309UM/D MOTOROLA...
Page 422 TLIE bit 7-26 TRNE bit 8-13 TME bit 10-8 TRST pin 11-5 TMIE bit 8-12 TSMA, TSMB registers 7-34 TMS pin 11-5 TSR register 7-34 TMS signal 2-36 TUE bit 7-29 TO bit 10-9 TX2, TX1, TX0 registers 7-34 MOTOROLA DSP56309UM/D I-13...
Page 423 XDB 1-13 XTAL 2-8 XTAL Disable bit (XTLD) 4-18 XTLD bit 4-18 Y data RAM 3-7 Y Memory Address Bus (YAB) 1-13 Y Memory Data Bus (YDB) 1-13 Y Memory Expansion Bus 1-13 YAB 1-13 YDB 1-13 I-14 DSP56309UM/D MOTOROLA...
Page 424: Signal/Connection Descriptions
DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX...
Page 425: Memory Configuration
DSP56309 OVERVIEW SIGNAL/CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I/O HOST INTERFACE (HI08) ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE (SCI) TIMER MODULE ON-CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX...

Motorola DSP56309 User Manual

Table of Contents

Dsp56309 Overview

List of Figures

Section 2 Signal/Connection Descriptions

Section 4 Core Configuration

Section 6 Host Interface (Hi08)

Section 9 Triple Timer Module

Section 10 On-Chip Emulation Module

Section 11 Jtag Port

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Summary of Contents for Motorola DSP56309