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3 SPECIFICATIONS
3.3 I/O Signals for the PLC CPU
3.3.1 List of I/O signals
Input signal (Signal direction QD62(E/D)
Device No.
X00
X01
Counter value large (point No. 1)
X02
Counter value coincidence (point No. 1)
X03
Counter value small (point No. 1)
CH1
X04
External preset request detection
X05
Counter value large (point No. 2)
X06
Counter value coincidence (point No. 2)
X07
Counter value small (point No. 2)
X08
Counter value large (point No. 1)
X09
Counter value coincidence (point No. 1)
X0A
Counter value small (point No. 1)
X0B
CH2
External preset request detection
X0C
Counter value large (point No. 2)
X0D
Counter value coincidence (point No. 2)
X0E
Counter value small (point No. 2)
X0F
Fuse broken detection flag
3 - 5
The I/O signals for the QD62(E/D) PLC CPU are listed in the table below.
For the I/O numbers (X/Y) and I/O addresses indicated in this and succeeding
sections, it is assumed that the QD62(E/D) is mounted into I/O slot 0 of the standard
base module.
PLC CPU)
Signal name
Module ready
Output signal (Signal direction PLC CPU
Device No.
Y00
Coincidence signal No. 1 reset command
Y01
Y02
Coincidence signal enable command
Y03
CH1
Y04
Y05
External preset detection reset command
Y06
Counter function selection start command
Y07
Coincidence signal No. 2 reset command
Y08
Coincidence signal No. 1 reset command
Y09
Y0A
Coincidence signal enable command
Y0B
CH2
Y0C
Y0D
External preset detection reset command
Y0E
Counter function selection start command
Y0F
Coincidence signal No. 2 reset command
MELSEC-Q
QD62(E/D))
Signal name
Preset command
Down count command
Count enable command
Preset command
Down count command
Count enable command
3 - 5
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