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Base Address
Register
FF65_0088
GPTCOMP2
FF65_008C
GPTCOMP3
FF65_0090
GPTCOMP4
FF65_0094 -
FF65_00BC
FF65_00C0
GPTMASK0
FF65_00C4
GPTMASK1
FF65_00C8
GPTMASK2
FF65_00CC
GPTMASK3
FF65_00D0
GPTMASK4
FF65_00D4 -
FF65_00FC
FF50_9080
CPRCAPTEVNT
9.1.2 Programmability
The GPT is fully programmable through memory mapped registers. Programmability features include:
• Programmable time base register (sets the Time Base Counter)
• Maskable time-base comparison support for each compare timer
• Programmable compare timer values
• Enable/disable control of all capture timers
• Enable/disable control of all capture and compare interrupts
• Mask control of interrupt status bits
• Programmable capture event edge detection and synchronization
9.2 Mode of Operation
9.2.1 Time Base Counter
The GPT time-base is provided by the 32-bit Time Base Counter (TBC) register. The TBC continually incre-
ments once every CPC700 SYS_CLOCK unless written or reset. The TBC provides the reference time for
all capture and compare timers. When the TBC is at its maximum value (all bits set to 1) it will roll back to
zero upon the next clock. The TBC may be read and written by software using its memory mapped
address.
The TBC is synchronously reset to zero upon a CPC700 reset or when either the GPT_RST or
GPT_TBC_RST bits are set in the CPRRESET register. Refer to Section 6.5.2, "Peripheral Reset Control
Register (CPRRESET)" for details.
9-2
Table 96. GPT Registers (Continued)
Register Name
GPT Compare Timer 2
GPT Compare Timer 3
GPT Compare Timer 4
(Reserved)
Compare Mask (Compare Timer 0)
Compare Mask (Compare Timer 1)
Compare Mask (Compare Timer 2)
Compare Mask (Compare Timer 3)
Compare Mask (Compare Timer 4)
(Reserved)
GPT Capture Event Generation
Access
Width
Mode
(bits)
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
General Purpose Timers
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