Table of Contents
Advertisement
Description
This section provides information about the Model 60 implementation
of the Micro Channel architecture, memory subsystem, and
| miscellaneous system ports.
Additional information on these topics
| can be found in the Hardware Interface Technical Reference listed in
| the preface of this manual.
| Micro Channel implementation
The POST routines and registers used to implement programmable
features of the Micro Channel architecture may vary from system to
system.
This section provides information about the Model 60
implementation of the Micro Channel architecture.
| Exception Reporting
| Exceptions should be reported using the asynchronous channel check
{ procedure.
The synchronous channel check procedure is not
| supported.
Adapter Identification
When the system is powered on, an adapter can issue an ID of hex
0000 for up to 1 second after channel reset to indicate it is not ready.
Any adapter that continues to issue an adapter ID of hex 0000 (not
ready) for more than 1 second is considered defective.
On the Mode!
60, if the channel reset was caused by a keyboard sequence or a
program routine, this time is reduced to 740 milliseconds.
Central Arbiter
The central arbitration control point gives intelligent subsystems on
the channel the ability to share and control the system.
It allows
burst data transfers and prioritization of control between devices.
This arbiter supports up to 16 arbitrating devices.
Model 60 System Board
— October 1990
3-3
Advertisement
Table of Contents
