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2.10.1 Service processor base
The PPC405 core is 5-stage pipeline instruction processor and contains 32-bit general
purpose registers. The Flash ROM contains a compressed image of a software load.
The SP base unit offers the following connections:
Two Ethernet Media Access Controller3 (MAC3) cores, which is a generic implementation
of the Ethernet Media Access (MAC) protocol compliant with ANSI/IEEE 802.3, IEEE
802.3u, ISO/IEC 8802.3 CSMA/CD standard. The Ethernet MAC3 supports both half
duplex (CSMA/CD) and full duplex operation at 10/100 Mbps. Both Ethernet port are
visible only to the service processor.
Two service processor communications interfaces, accessible only though the service
processor communications ports of OpenPower 720 on the rear side. At the time of
writing, the System Management Interface (SMI) is usable if a connection is established to
service processor communications port 1. Terminals connected to service processor
communications port 2 receive only boot sequence information without manual interaction.
When the HMC is connected to the SP, the service processor communications ports are
disabled and do not provide any external connection.
2.10.2 Service processor extender
The SP extender unit offers two system power control network (SPCN) ports that are used to
control the power of the attached I/O subsystems. The SPCN control software and the service
processor software are run on the same PPC405 processor.
2.11 Boot process
With the implementation of the POWER5 chip technology in the pSeries platform, the boot
process is enhanced for the flexibility that the POWER5 processor-based hardware features.
Depending on the customer configuration, a system may or may not require the use of an
HMC to manage the system. The boot process, based on the Initial Program Load (IPL)
setup, will depend on the hardware setup and on the way we will use the features that
POWER5 processor-based systems provide.
The IPL process starts when power is connected to the system. Immediately after, the SP
starts an internal self test based on integrated diagnostic programs (Built-In-Self-Test, BIST).
Only if all the test units have been successfully passed, the system status changes to
standby.
2.11.1 IPL flow without an HMC attached to the system
When the system status is standby, the SP provides a System Management Interface (SMI)
that can be accessed by pressing any key on an attached serial console keyboard, or the
Advanced System Management Interface (ASMI) using a Web browser
that is connected to the SP on an Ethernet network.
The SP and the ASMI are standard on all POWER5 processor-based hardware. Both system
management interfaces require you to enter the general or admin ID password and allow you
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OpenPower 720 Technical Overview and Introduction
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on a client system
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