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HCD-VX555/VX555J
• IC502 M30622MGA-A45FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No.
Pin Name
I/O
1
SENSE
2
SENSE CLK
O
3
RESOLUTION
O
4
CHROMA LEVEL
O
5
DSP CLK
O
6
TSENS
—
7
REMOTE IN
—
8
BYTE
9
CN VSS
—
10
DSP MUTE
O
11
CTRL1
O
12
XRESET
13
XOUT
O
14
VSS
—
15
XIN
16
VCC
—
17
NMI
18
SCOR
19
DSENS
—
20
CL680INTERRUPT
21
H.SYNC IN
22
BGP
O
23
—
24
PWM3(BD)
O
25
—
26
PWM2(BD)
O
27
—
28
PWM1(BD)
O
29
12C.CLK
I/O
30
12C.DATA
I/O
31
DATA1O
O
32
DATA1I
33
CLK1
O
34
RTS1
O
35
DATAO
O
36
DATAI
37
CLK1
38
P.ON
—
39
BUS XRDY
40
BUS
—
41
BUS XHOLD
42, 43
BUS
—
44
OSD.LANGUAGE
45
VSYNC
46
BUS XWRL
O
47
LO.BOOST
—
48
AUDIO MUTE
—
49
LOAD OUT
—
50
LOAD IN
—
51
INSW
—
56
I
Internal status (SENSE) signal input from the CXD3068Q (IC101)
Sense serial data reading clock signal output to the CXD3068Q (IC101)
Y resolution output
Chroma level output
Serial data transfer clock signal output to the CXD3068Q (IC101)
Not used (open)
Not used (open)
I
External data bus line byte selection signal input "L": 16 bit, "H": 8 bit (fixed at "L")
Ground terminal
Muting on/off control signal output to the CXD3068Q (IC101) "H": muting on
Clock selection signal output to the CXD3068Q (IC101) "L": 16.9344 MHz (double speed), "H": 33.8688 MHz
Reset signal input from the system controller (IC501) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
Main system clock output terminal (10 MHz)
Ground terminal
I
Main system clock input terminal (10 MHz)
Power supply terminal (+5V)
I
Non-maskable interrupt input terminal (fixed at "H" in this set)
I
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC101)
Not used (open)
I
Interrupt request signal input from the CL680 (IC505)
I
Horizontal sync signal input
Burst gate pulse signal output
Not used (open)
PWM3 signal output to the CXA2581N (IC103)
Not used (open)
PWM2 signal output to the CXA2581N (IC103)
Not used (open)
PWM1 signal output to the CXA2581N (IC103)
2
I
C clock signal
I
2
C data signal
Serial data output to the FLASH writer
I
Serial data input from the FLASH writer
Serial data transfer clock signal output to the FLASH writer
RTS signal to the FLASH writer
Serial data0 output to the CL680 (IC505)
I
Serial data0 input from the CL680 (IC505)
I
Data reading clock signal input from the CL680 (IC505)
Not used (open)
I
Ready signal input terminal Not used (fixed at "H")
Not used (open)
I
Hold signal input terminal from the FLASH writer
Not used (open)
I
OSD language select input terminal "H": English, "L": China
I
Vertical sync signal input
Bus write signal output to the FLASH writer
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (fixed at "H")
Description
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