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MiCOM P144 Agile
GE MiCOM P144 Agile Manuals
Manuals and User Guides for GE MiCOM P144 Agile. We have
1
GE MiCOM P144 Agile manual available for free PDF download: Technical Manual
GE MiCOM P144 Agile Technical Manual (668 pages)
Feeder Management IED
Brand:
GE
| Category:
Control Unit
| Size: 21.79 MB
Table of Contents
Table of Contents
3
Chapter 1 Introduction
27
Rear Serial Port
28
Chapter Overview
29
Trip Circuit Supervision Scheme
29
Cip
29
Foreword
30
Target Audience
30
Typographical Conventions
30
Cip
30
Nomenclature
31
Cip
31
Product Scope
32
Ordering Options
32
Cip
32
Features and Functions
33
Protection Functions
33
Control Functions
34
Measurement Functions
34
Communication Functions
34
Compliance
36
Functional Overview
37
Figure 1: Functional Overview
37
Chapter 2 Safety Information
39
Chapter Overview
41
Health and Safety
42
Symbols
43
Installation, Commissioning and Servicing
44
Lifting Hazards
44
Electrical Hazards
44
UL/CSA/CUL Requirements
45
Fusing Requirements
45
Equipment Connections
46
Protection Class 1 Equipment Requirements
46
Pre-Energisation Checklist
47
Peripheral Circuitry
47
Upgrading/Servicing
48
Decommissioning and Disposal
49
Regulatory Compliance
50
EMC Compliance: 2014/30/EU
50
LVD Compliance: 2014/35/EU
50
R&TTE Compliance: 2014/53/EU
50
UL/CUL Compliance
50
ATEX Compliance: 2014/34/EU
50
Chapter 3 Hardware Design
53
Chapter Overview
55
Hardware Architecture
56
Figure 2: Hardware Architecture
56
Mechanical Implementation
57
Housing Variants
57
Figure 3: Exploded View of IED
57
List of Boards
58
Front Panel
59
Front Panel Compartments
59
Figure 4: Front Panel (60TE)
59
HMI Panel
60
Front Serial Port (SK1)
60
Figure 5: HMI Panel
60
Front Parallel Port (SK2)
61
Fixed Function Leds
61
Function Keys
61
Programable Leds
62
Rear Panel
63
Figure 6: Rear View of Populated Case
63
Figure 7: Terminal Block Types
64
Boards and Modules
65
Pcbs
65
Subassemblies
65
Figure 8: Rear Connection to Terminal Block
65
Main Processor Board
66
Figure 9: Main Processor Board
66
Power Supply Board
67
Figure 10: Power Supply Board
67
Figure 11: Power Supply Assembly
68
Watchdog
69
Figure 12: Power Supply Terminals
69
Rear Serial Port
70
Figure 13: Watchdog Contact Terminals
70
Input Module - 1 Transformer Board
71
Figure 14: Rear Serial Port Terminals
71
Figure 15: Input Module - 1 Transformer Board
71
Input Module Circuit Description
72
Figure 16: Input Module Schematic
72
Transformer Board
73
Figure 17: Transformer Board
73
Input Board
74
Figure 18: Input Board
74
Standard Output Relay Board
75
Figure 19: Standard Output Relay Board - 8 Contacts
75
IRIG-B Board
76
Figure 20: IRIG-B Board
76
Fibre Optic Board
77
Figure 21: Fibre Optic Board
77
Rear Communication Board
78
Ethernet Board
78
Figure 22: Rear Communication Board
78
Figure 23: Ethernet Board
78
Redundant Ethernet Board
80
Figure 24: Redundant Ethernet Board
80
Chapter 4 Software Design
83
Chapter Overview
85
Sofware Design Overview
86
Figure 25: Software Architecture
86
System Level Software
87
Real Time Operating System
87
System Services Software
87
Self-Diagnostic Software
87
Startup Self-Testing
87
System Boot
87
System Level Software Initialisation
88
Platform Software Initialisation and Monitoring
88
Continuous Self-Testing
88
Platform Software
89
Record Logging
89
Settings Database
89
Interfaces
89
Protection and Control Functions
90
Acquisition of Samples
90
Frequency Tracking
90
Direct Use of Sample Values
90
Fourier Signal Processing
90
Programmable Scheme Logic
91
Figure 26: Frequency Response (Indicative Only)
91
Event Recording
92
Disturbance Recorder
92
Fault Locator
92
Function Key Interface
92
Chapter 5 Configuration
93
Chapter Overview
95
Settings Application Software
96
Using the HMI Panel
97
Navigating the HMI Panel
98
Getting Started
98
Figure 27: Navigating the HMI
98
Default Display
99
Default Display Navigation
100
Figure 28: Default Display Navigation
100
Password Entry
101
Processing Alarms and Records
101
Menu Structure
102
Changing the Settings
103
Direct Access (the Hotkey Menu)
104
Setting Group Selection Using Hotkeys
104
Control Inputs
104
Circuit Breaker Control
105
Function Keys
105
Date and Time Configuration
107
Using an SNTP Signal
107
Using an IRIG-B Signal
107
Using an IEEE 1588 PTP Signal
107
Without a Timing Source Signal
108
Time Zone Compensation
108
Daylight Saving Time Compensation
109
Settings Group Selection
110
Chapter 6 Current Protection Functions
111
Chapter Overview
113
Overcurrent Protection Principles
114
IDMT Characteristics
114
IEC 60255 IDMT Curves
115
European Standards
117
Figure 29: IEC 60255 IDMT Curves
117
North American Standards
118
IEC and IEEE Inverse Curves
120
Figure 30: IEC Standard and very Inverse Curves
120
Figure 31: IEC Extremely Inverse and IEEE Moderate Inverse Curves
120
Differences between the North American and European Standards
121
Programmable Curves
121
Principles of Implementation
121
Figure 32: IEEE very and Extremely Inverse Curves
121
Timer Hold Facility
122
Figure 33: Principle of Protection Function Implementation
122
Phase Overcurrent Protection
124
Phase Overcurrent Protection Implementation
124
Non-Directional Overcurrent Logic
125
Figure 34: Non-Directional Overcurrent Logic Diagram
125
Directional Element
126
Directional Overcurrent Logic
127
Figure 35: Directional Overcurrent Logic Diagram (Phase a Shown Only)
127
Application Notes
128
Parallel Feeders
128
Figure 36: Typical Distribution System Using Parallel Transformers
128
Ring Main Arrangements
129
Setting Guidelines
129
Figure 37: Typical Ring Main with Associated Overcurrent Protection
129
Setting Guidelines (Directional Element)
130
Voltage Dependent Overcurrent Element
131
Voltage Dependent Overcurrent Protection Implementation
131
Voltage Controlled Overcurrent Protection
131
Figure 38: Modification of Current Pickup Level for Voltage Controlled Overcurrent Protection
131
Voltage Restrained Overcurrent Protection
132
Figure 39: Modification of Current Pickup Level for Voltage Restrained Overcurrent Protection
132
Voltage Dependent Overcurrent Logic
133
Application Notes
133
Setting Guidelines
133
Figure 40: Voltage Dependant Overcurrent Logic (Phase a to Phase B)
133
Current Setting Threshold Selection
135
Figure 41: Selecting the Current Threshold Setting
135
Cold Load Pickup
136
Implementation
136
CLP Logic
137
Application Notes
137
CLP for Resistive Loads
137
CLP for Motor Feeders
137
Figure 42: Cold Load Pickup Logic
137
CLP for Switch Onto Fault Conditions
138
Selective Logic
139
Selective Logic Implementation
139
Selective Logic Diagram
139
Figure 43: Selective Logic
139
Timer Setting Selection
141
Figure 44: Selecting the Timer Settings
141
Negative Sequence Overcurrent Protection
142
Negative Sequence Overcurrent Protection Implementation
142
Non-Directional Negative Sequence Overcurrent Logic
143
Composite Earth Fault Start Logic
143
Directional Element
143
Figure 45: Negative Sequence Overcurrent Logic - Non-Directional Operation
143
Figure 46: Composite Earth Fault Start Logic
143
Directional Negative Sequence Overcurrent Logic
144
Application Notes
144
Setting Guidelines (Current Threshold)
144
Figure 47: Negative Sequence Overcurrent Logic - Directional Operation
144
Setting Guidelines (Time Delay)
145
Setting Guidelines (Directional Element)
145
Earth Fault Protection
146
Earth Fault Protection Elements
146
Non-Directional Earth Fault Logic
147
IDG Curve
147
Figure 48: Non-Directional EF Logic (Single Stage)
147
Directional Element
148
Residual Voltage Polarisation
148
Figure 49: IDG Characteristic
148
Negative Sequence Polarisation
149
Figure 50: Directional EF Logic with Neutral Voltage Polarization (Single Stage)
149
Application Notes
150
Setting Guidelines (Directional Element)
150
Peterson Coil Earthed Systems
150
Figure 51: Directional Earth Fault Logic with Negative Sequence Polarisation (Single Stage)
150
Figure 52: Current Level (Amps) at Which Transient Faults Are Self-Extinguishing
151
Figure 53: Earth Fault in Petersen Coil Earthed System
151
Figure 54: Distribution of Currents During a Phase C Fault
152
Figure 55: Phasors for a Phase C Earth Fault in a Petersen Coil Earthed System
152
Figure 56: Zero Sequence Network Showing Residual Currents
153
Setting Guidelines (Compensated Networks)
154
Figure 57: Phase C Earth Fault in Petersen Coil Earthed System: Practical Case with Resistance
154
Sensitive Earth Fault Protection
156
SEF Protection Implementation
156
Non-Directional SEF Logic
156
Figure 58: Non-Directional SEF Logic
156
SEF any Start Logic
157
EPATR B Curve
157
Figure 59: SEF any Start Logic
157
Directional Element
158
Figure 60: EPATR B Characteristic Shown for TMS = 1.0
158
Figure 61: Types of Directional Control
158
Wattmetric Characteristic
159
Figure 62: Resistive Components of Spill Current
159
Icos Phi / Isin Phi Characteristic
160
Figure 63: Operating Characteristic for Icos
160
Directional SEF Logic
161
Figure 64: Directional SEF with VN Polarisation (Single Stage)
161
Application Notes
162
Insulated Systems
162
Figure 65: Current Distribution in an Insulated System with C Phase Fault
162
Setting Guidelines (Insulated Systems)
163
Figure 66: Phasor Diagrams for Insulated System with C Phase Fault
163
Figure 67: Positioning of Core Balance Current Transformers
164
Thermal Overload Protection
165
Single Time Constant Characteristic
165
Dual Time Constant Characteristic
165
Thermal Overload Protection Implementation
166
Thermal Overload Protection Logic
166
Application Notes
166
Setting Guidelines for Dual Time Constant Characteristic
166
Figure 68: Thermal Overload Protection Logic Diagram
166
Figure 69: Spreadsheet Calculation for Dual Time Constant Thermal Characteristic
167
Figure 70: Dual Time Constant Thermal Characteristic
167
Setting Guidelines for Single Time Constant Characteristic
168
Broken Conductor Protection
170
Broken Conductor Protection Implementation
170
Broken Conductor Protection Logic
170
Application Notes
170
Setting Guidelines
170
Figure 71: Broken Conductor Logic
170
Blocked Overcurrent Protection
172
Blocked Overcurrent Implementation
172
Blocked Overcurrent Logic
172
Blocked Earth Fault Logic
172
Figure 72: Blocked Overcurrent Logic
172
Application Notes
173
Busbar Blocking Scheme
173
Figure 73: Blocked Earth Fault Logic
173
Figure 74: Simple Busbar Blocking Scheme
173
Figure 75: Simple Busbar Blocking Scheme Characteristics
174
Second Harmonic Blocking
175
Second Harmonic Blocking Implementation
175
Second Harmonic Blocking Logic (POC Input)
176
Figure 76: 2Nd Harmonic Blocking Logic (POC Input)
176
Second Harmonic Blocking Logic (SEF Input)
177
Application Notes
177
Setting Guidelines
177
Figure 77: 2Nd Harmonic Blocking Logic (SEF Input)
177
Load Blinders
178
Load Blinder Implementation
178
Figure 78: Load Blinder and Angle
178
Load Blinder Logic
179
Figure 79: Load Blinder Logic 3Phase
179
Figure 80: Load Blinder Logic Phase a
180
Neutral Admittance Protection
182
Neutral Admittance Operation
182
Conductance Operation
182
Figure 81: Admittance Protection
182
Susceptance Operation
183
Figure 82: Conductance Operation
183
Figure 83: Susceptance Operation
183
Busbar Protection
185
Figure 84: Simplified Busbar Representation
185
Buswire Supervision
186
Figure 85: High Impedance Differential Protection for Busbars
186
Chapter 7 Restricted Earth Fault Protection
187
Chapter Overview
189
REF Protection Principles
190
Figure 86: REF Protection for Delta Side
190
Figure 87: REF Protection for Star Side
190
Resistance-Earthed Star Windings
191
Solidly-Earthed Star Windings
191
Figure 88: REF Protection for Resistance-Earthed Systems
191
Through Fault Stability
192
Restricted Earth Fault Types
192
Figure 89: REF Protection for Solidly Earthed System
192
Low Impedance REF Principle
193
Figure 90: Low Impedance REF Connection
193
High Impedance REF Principle
194
Figure 91: Three-Slope REF Bias Characteristic
194
Figure 92: High Impedance REF Principle
195
Figure 93: High Impedance REF Connection
196
Restricted Earth Fault Protection Implementation
197
Low Impedance REF
197
Setting the Bias Characteristic
197
Delayed Bias
198
Transient Bias
198
High Impedance REF
198
Figure 94: REF Bias Characteristic
198
High Impedance REF Calculation Principles
199
Application Notes
200
Star Winding Resistance Earthed
200
Figure 95: Star Winding, Resistance Earthed
200
Low Impedance REF Protection Application
201
Setting Guidelines for Biased Operation
201
Low Impedance REF Scaling Factor
201
Figure 96: Percentage of Winding Protected
201
Parameter Calculations
202
Figure 97: Low Impedance REF Scaling Factor
202
High Impedance REF Protection Application
203
High Impedance REF Operating Modes
203
Figure 98: Hi-Z REF Protection for a Grounded Star Winding
203
Figure 99: Hi-Z REF Protection for a Delta Winding
203
Setting Guidelines for High Impedance Operation
204
Figure 100: Hi-Z REF Protection for Autotransformer Configuration
204
Figure 101: High Impedance REF for the LV Winding
205
Chapter 8 CB Fail Protection
207
Chapter Overview
209
Circuit Breaker Fail Protection
210
Circuit Breaker Fail Implementation
211
Circuit Breaker Fail Timers
211
Zero Crossing Detection
211
Circuit Breaker Fail Logic
213
Figure 102: Circuit Breaker Fail Logic - Three Phase Start
213
Figure 103: Circuit Breaker Fail Logic - Single Phase Start
214
Figure 104: Circuit Breaker Fail Trip and Alarm
215
Undercurrent and ZCD Logic for CB Fail
216
Figure 105: Undercurrent and Zero Crossing Detection Logic for CB Fail
216
CB Fail SEF Protection Logic
217
Figure 106: CB Fail SEF Protection Logic
217
CB Fail Non Current Protection Logic
218
Figure 107: CB Fail Non Current Protection Logic
218
Circuit Breaker Mapping
219
Figure 108: Circuit Breaker Mapping
219
Application Notes
220
Reset Mechanisms for CB Fail Timers
220
Setting Guidelines (CB Fail Timer)
220
Setting Guidelines (Undercurrent)
221
Figure 109: CB Fail Timing
221
Chapter 9 Current Transformer Requirements
223
Chapter Overview
225
CT Requirements
226
Phase Overcurrent Protection
226
Directional Elements
226
Non-Directional Elements
226
Earth Fault Protection
227
Directional Elements
227
Non-Directional Elements
227
SEF Protection (Residually Connected)
227
SEF Protection (Core-Balanced CT)
228
Directional Elements
228
Non-Directional Elements
228
Low Impedance REF Protection
228
High Impedance REF Protection
228
High Impedance Busbar Protection
229
Use of Metrosil Non-Linear Resistors
229
Use of ANSI C-Class Cts
231
Chapter 10 Voltage Protection Functions
233
Chapter Overview
235
Undervoltage Protection
236
Undervoltage Protection Implementation
236
Undervoltage Protection Logic
237
Figure 110: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)
237
Application Notes
238
Undervoltage Setting Guidelines
238
Overvoltage Protection
239
Overvoltage Protection Implementation
239
Overvoltage Protection Logic
240
Figure 111: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)
240
Application Notes
241
Overvoltage Setting Guidelines
241
Rate of Change of Voltage Protection
242
Rate of Change of Voltage Protection Implementation
242
Rate of Change of Voltage Logic
242
Figure 112: Rate of Change of Voltage Protection Logic
242
Residual Overvoltage Protection
244
Residual Overvoltage Protection Implementation
244
Residual Overvoltage Logic
245
Application Notes
245
Calculation for Solidly Earthed Systems
245
Figure 113: Residual Overvoltage Logic
245
Calculation for Impedance Earthed Systems
246
Figure 114: Residual Voltage for a Solidly Earthed System
246
Neutral Voltage Displacement (Nvd) Protection Applied to Condenser Bushings (Capacitor Cones)
247
Figure 115: Residual Voltage for an Impedance Earthed System
247
Figure 116: Star Connected Condenser Bushings
248
Figure 117: Theoretical Earth Fault in Condenser Bushing System
248
Figure 118: Condenser Bushing System Vectors
249
Figure 119: Device Connection with Resistors and Shorting Contact
250
Figure 120: Device Connection P141/ P142/ P143/ P145
252
Figure 121: Device Connection P144
252
Setting Guidelines
253
Negative Sequence Overvoltage Protection
254
Negative Sequence Overvoltage Implementation
254
Negative Sequence Overvoltage Logic
254
Application Notes
254
Setting Guidelines
254
Figure 122: Negative Sequence Overvoltage Logic
254
Sensitive Overvoltage Supervision
256
Sensitive Overvoltage Implementation
256
Sensitive Overvoltage Filter Mode
256
Sensitive Overvoltage Logic
257
Sensitive Overvoltage Operation Logic
257
Figure 123: Sensitive Overvoltage Operation Logic
257
Sensitive Overvoltage Filter Mode Logic
258
Sensitive Overvoltage Blocking Logic
258
Figure 124: Sensitive Overvoltage Filter Mode Logic
258
Figure 125: Sensitive Overvoltage Blocking Logic
258
Chapter 11 Frequency Protection Functions
259
Chapter Overview
261
Frequency Protection Overview
262
Frequency Protection Implementation
262
Underfrequency Protection
264
Underfrequency Protection Implementation
264
Underfrequency Protection Logic
264
Figure 126: Underfrequency Logic (Single Stage)
264
Application Notes
265
Setting Guidelines
265
Overfrequency Protection
266
Overfrequency Protection Implementation
266
Overfrequency Protection Logic
266
Figure 127: Overfrequency Logic (Single Stage)
266
Application Notes
267
Setting Guidelines
267
Figure 128: Power System Segregation Based Upon Frequency Measurements
267
Independent R.O.C.O.F Protection
268
Indepenent R.O.C.O.F Protection Implementation
268
Independent R.O.C.O.F Protection Logic
269
Application Notes
269
Setting Guidelines
269
Figure 129: Independent Rate of Change of Frequency Logic (Single Stage)
269
Frequency-Supervised R.O.C.O.F Protection
271
Frequency-Supervised R.O.C.O.F Implementation
271
Frequency-Supervised R.O.C.O.F Logic
272
Application Notes
272
Frequency-Supervised R.O.C.O.F Example
272
Figure 130: Frequency-Supervised Rate of Change of Frequency Logic (Single Stage)
272
Setting Guidelines
273
Figure 131: Frequency Supervised Rate of Change of Frequency Protection
273
Average Rate of Change of Frequency Protection
274
Average R.O.C.O.F Protection Implementation
274
Figure 132: Average Rate of Change of Frequency Characteristic
274
Average R.O.C.O.F Logic
275
Application Notes
275
Setting Guidelines
275
Figure 133: Average Rate of Change of Frequency Logic (Single Stage)
275
Load Shedding and Restoration
277
Load Restoration Implementation
277
Holding Band
277
Figure 134: Load Restoration with Short Deviation into Holding Band
278
Figure 135: Load Restoration with Long Deviation into Holding Band
279
Load Restoration Logic
280
Application Notes
280
Setting Guidelines
280
Figure 136: Load Restoration Logic
280
Chapter 12 Power Protection Functions
283
Chapter Overview
285
Overpower Protection
286
Overpower Protection Implementation
286
Overpower Logic
287
Application Notes
287
Forward Overpower Setting Guidelines
287
Reverse Power Considerations
287
Figure 137: Overpower Logic
287
Reverse Overpower Setting Guidelines
288
Underpower Protection
289
Underpower Protection Implementation
289
Underpower Logic
290
Application Notes
290
Low Forward Power Considerations
290
Low Forward Power Setting Guidelines
290
Figure 138: Underpower Logic
290
Sensitive Power Protection
292
Sensitive Power Protection Implementation
292
Sensitive Power Measurements
292
Sensitive Power Logic
293
Application Notes
293
Sensitive Power Calculation
293
Figure 139: Sensitive Power Logic Diagram
293
Figure 140: Sensitive Power Input Vectors
294
Sensitive Power Setting Guidelines
295
Transient Earth Fault Detection
296
Transient Earth Fault Detection Implementation
297
Transient Earth Fault Detector
297
Fault Type Detector
297
Direction Detector
297
Transient Earth Fault Detection Logic
298
Transient Earth Fault Detection Logic Overview
298
Figure 141: Transient Earth Fault Logic Overview
298
Fault Type Detector Logic
299
Direction Detector Logic - Standard Mode
299
Transient Earth Fault Detection Output Alarm Logic
299
Figure 142: Fault Type Detector Logic
299
Figure 143: Direction Detector Logic - Standard Mode
299
Figure 144: TEFD Output Alarm Logic
299
Chapter 13 Autoreclose
301
Chapter Overview
303
Introduction to 3-Phase Autoreclose
304
Implementation
305
Autoreclose Function Inputs
306
CB Healthy
306
Block AR
306
Reset Lockout
306
AR Auto Mode
306
Auto Mode
306
Liveline Mode
306
Telecontrol Mode
306
Circuits OK
306
AR Sys Checks OK
307
Ext AR Prot Trip (External AR Protection Trip)
307
Ext AR Prot Start (External AR Protection Start)
307
DAR Complete (Delayed Autoreclose Complete)
307
CB in Service (Circuit Breaker in Service)
307
AR Restart
307
DT OK to Start (Dead Time OK to Start)
307
Deadtime Enabled
308
AR Init Triptest (Initiate Trip Test)
308
AR Skip Shot
308
Inh Reclaim Time (Inhibit Reclaim Time)
308
Autoreclose Function Outputs
309
AR in Progress
309
AR in Progress 1 (DAR in Progress)
309
Sequence Counter Status DDB Signals
309
Successful Close
309
AR in Service
309
Block Main Prot (Block Main Protection)
309
Block SEF Prot (Block SEF Protection)
309
Reclose Checks
309
Deadt in Prog (Dead Time in Progress)
310
DT Complete (Dead Time Complete)
310
AR Sync Check (AR Synchronisation Check)
310
AR Syschecks OK (AR System Checks OK)
310
Auto Close
310
Protection Lockt (Protection Lockout)
310
Reset Lckout Alm (Reset Lockout Alarm)
310
Reclaim in Prog
310
Reclaim Complete
310
Autoreclose Function Alarms
311
AR no Sys Check
311
AR CB Unhealthy
311
AR Lockout
311
Autoreclose Operation
312
Operating Modes
313
Four-Position Selector Switch Implementation
313
Figure 145: Four-Position Selector Switch Implementation
314
Operating Mode Selection Logic
315
Autoreclose Initiation
315
Figure 146: Autoreclose Mode Select Logic
315
Start Signal Logic
317
Trip Signal Logic
317
Figure 147: Start Signal Logic
317
Figure 148: Trip Signal Logic
317
Blocking Signal Logic
318
Shots Exceeded Logic
318
Figure 149: Blocking Signal Logic
318
Figure 150: Shots Exceeded Logic
318
AR Initiation Logic
319
Blocking Instantaneous Protection for Selected Trips
319
Figure 151: AR Initiation Logic
319
Figure 152: Blocking Instantaneous Protection for Selected Trips
320
Blocking Instantaneous Protection for Lockouts
321
Dead Time Control
322
Figure 153: Blocking Instantaneous Protection for Lockouts
322
AR CB Close Control
323
Figure 154: Dead Time Control Logic
323
AR System Checks
324
Figure 155: AR CB Close Control Logic
324
Reclaim Timer Initiation
325
Figure 156: AR System Check Logic
325
Autoreclose Inhibit
326
Figure 157: Reclaim Time Logic
326
Autoreclose Lockout
327
Figure 158: AR Initiation Inhibit
327
Figure 159: Overall Lockout Logic
328
Sequence Co-Ordination
329
Figure 160: Lockout for Protection Trip When AR Is Not Available
329
System Checks for First Reclose
330
Setting Guidelines
331
Number of Shots
331
Dead Timer Setting
331
Stability and Synchronism Requirements
331
Operational Convenience
331
Load Requirements
332
Circuit Breaker
332
Fault De-Ionisation Time
332
Protection Reset Time
332
Reclaim Timer Setting
333
Chapter 14 Monitoring and Control
335
Chapter Overview
337
Event Records
338
Event Types
338
Opto-Input Events
339
Contact Events
339
Alarm Events
339
Fault Record Events
340
Maintenance Events
340
Protection Events
340
Figure 161: Fault Recorder Stop Conditions
340
Security Events
341
Platform Events
341
Disturbance Recorder
342
Measurements
343
Measured Quantities
343
Measured and Calculated Currents
343
Measured and Calculated Voltages
343
Power and Energy Quantities
343
Demand Values
344
Frequency Measurements
344
Other Measurements
344
Measurement Setup
344
Fault Locator
345
Fault Locator Settings Example
345
Opto-Input Time Stamping
345
CB Condition Monitoring
346
Application Notes
346
Setting the Thresholds for the Total Broken Current
346
Setting the Thresholds for the Number of Operations
346
Setting the Thresholds for the Operating Time
347
Setting the Thresholds for Excesssive Fault Frequency
347
CB State Monitoring
348
CB State Monitoring Logic
349
Figure 162: CB State Monitoring Logic
349
Circuit Breaker Control
350
CB Control Using the IED Menu
350
CB Control Using the Hotkeys
351
CB Control Using the Function Keys
351
Figure 163: Hotkey Menu Navigation
351
CB Control Using the Opto-Inputs
352
Remote CB Control
352
Figure 164: Default Function Key PSL
352
Figure 165: Remote Control of Circuit Breaker
353
CB Control Logic
354
Synchronisation Check
354
CB Healthy Check
354
Figure 166: CB Control Logic
354
Pole Dead Function
355
Pole Dead Logic
355
Figure 167: Pole Dead Logic
355
System Checks
356
System Checks Implementation
356
VT Connections
356
Voltage Monitoring
356
Check Synchronisation
357
Check Syncronisation Vector Diagram
357
System Split
358
Figure 168: Check Synchronisation Vector Diagram
358
System Check Logic
359
Figure 169: System Check Logic
359
System Check PSL
360
Application Notes
360
Slip Control
360
Figure 170: System Check PSL
360
Use of Check Sync 2 and System Split
361
Predictive Closure of Circuit Breaker
361
Voltage and Phase Angle Correction
361
Switch Status and Control
363
Figure 171: Representation of Typical Feeder Bay
363
Switch Status Logic
364
Figure 172: Switch Status Logic
364
Switch Control Logic
365
Figure 173: Switch Control Logic
365
Chapter 15 Supervision
367
Chapter Overview
369
Voltage Transformer Supervision
370
Loss of One or Two Phase Voltages
370
Loss of All Three Phase Voltages
370
Absence of All Three Phase Voltages on Line Energisation
370
VTS Implementation
371
VTS Logic
371
Figure 174: VTS Logic
372
VTS Acceleration Indication Logic
373
Figure 175: VTS Acceleration Indication Logic
373
Current Transformer Supervision
374
CTS Implementation
374
CTS Logic
374
Figure 176: CTS Logic Diagram
374
Application Notes
375
Setting Guidelines
375
Trip Circuit Supervision
376
Trip Circuit Supervision Scheme
376
Resistor Values
376
Psl for Tcs Scheme 1
377
Trip Circuit Supervision Scheme 2
377
Figure 177: TCS Scheme
378
Figure 178: PSL for TCS Scheme
378
Figure 179: TCS Scheme
378
Figure 180: PSL for TCS Scheme 2
378
Figure 181: TCS Scheme 3
379
Figure 182: PSL for TCS Scheme 3
379
Chapter 16 Digital I/O and PSL Configuration
381
Chapter Overview
383
Configuring Digital Inputs and Outputs
384
Scheme Logic
385
Figure 183: Scheme Logic Interfaces
385
PSL Editor
386
PSL Schemes
386
PSL Scheme Version Control
386
Configuring the Opto-Inputs
387
Assigning the Output Relays
388
Fixed Function Leds
389
Trip LED Logic
389
Figure 184: Trip LED Logic
389
Configuring Programmable Leds
390
Function Keys
392
Control Inputs
393
Chapter 17 Electrical Teleprotection
395
Chapter Overview
397
Introduction
398
Teleprotection Scheme Principles
399
Direct Tripping
399
Permissive Tripping
399
Implementation
400
Configuration
401
Figure 185: Example Assignment of Intermicom Signals Within the PSL
402
Connecting to Electrical Intermicom
403
Short Distance
403
Long Distance
403
Figure 186: Direct Connection
403
Figure 187: Indirect Connection Using Modems
403
Application Notes
404
Chapter 18 Communications
407
Chapter Overview
409
Communication Interfaces
410
Serial Communication
411
EIA(RS)232 Bus
411
EIA(RS)485 Bus
411
EIA(RS)485 Biasing Requirements
412
K-Bus
412
Figure 188: RS485 Biasing Circuit
412
Figure 189: Remote Communication Using K-Bus
413
Standard Ethernet Communication
414
Hot-Standby Ethernet Failover
414
Redundant Ethernet Communication
415
Supported Protocols
415
Parallel Redundancy Protocol
416
Figure 190: IED Attached to Separate Lans
416
PRP Application in the Substation
417
High-Availability Seamless Redundancy (HSR)
417
HSR Multicast Topology
417
Figure 191: PRP Application in the Substation
417
HSR Unicast Topology
418
Figure 192: HSR Multicast Topology
418
HSR Application in the Substation
419
Figure 193: HSR Unicast Topology
419
Rapid Spanning Tree Protocol
420
Figure 194: HSR Application in the Substation
420
Figure 195: IED Attached to Redundant Ethernet Star or Ring Circuit
420
Self Healing Protocol
421
Figure 196: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities
421
Figure 197: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
421
Dual Homing Protocol
422
Figure 198: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
422
Figure 199: Dual Homing Mechanism
423
Configuring IP Addresses
424
Figure 200: Application of Dual Homing Star at Substation Level
424
Configuring the IED IP Address
425
Configuring the REB IP Address
425
Figure 201: IED and REB IP Address Configuration
425
Simple Network Management Protocol (SNMP)
429
SNMP Management Information Bases
429
Main Processor MIBS Structure
429
Redundant Ethernet Board MIB Structure
430
Accessing the MIB
434
Main Processor SNMP Configuration
434
Data Protocols
436
Courier
436
Physical Connection and Link Layer
436
Courier Database
437
Settings Categories
437
Setting Changes
437
Event Extraction
437
Disturbance Record Extraction
439
Programmable Scheme Logic Settings
439
Time Synchronisation
439
Courier Configuration
440
Physical Connection and Link Layer
441
Iec 60870-5-103
441
Initialisation
442
Time Synchronisation
442
Spontaneous Events
442
General Interrogation (GI)
442
Cyclic Measurements
442
Commands
442
Test Mode
443
Disturbance Records
443
Command/Monitor Blocking
443
IEC 60870-5-103 Configuration
443
Dnp
444
Physical Connection and Link Layer
445
Object 1 Binary Inputs
445
Object 10 Binary Outputs
445
Object 20 Binary Counters
446
Object 30 Analogue Input
446
Figure 202: Control Input Behaviour
446
Object 40 Analogue Output
447
Object 50 Time Synchronisation
447
DNP3 Device Profile
447
DNP3 Configuration
455
Modbus
456
Physical Connection and Link Layer
457
MODBUS Functions
457
Response Codes
457
Register Mapping
458
Event Extraction
458
Disturbance Record Extraction
459
Figure 203: Manual Selection of a Disturbance Record
462
Figure 204: Automatic Selection of Disturbance Record - Method 1
463
Figure 205: Automatic Selection of Disturbance Record - Method 2
464
Figure 206: Configuration File Extraction
465
Figure 207: Data File Extraction
466
Setting Changes
467
Password Protection
467
Protection and Disturbance Recorder Settings
467
Time Synchronisation
468
Power and Energy Measurement Data Formats
469
MODBUS Configuration
470
Iec 61850
471
Benefits of IEC 61850
471
IEC 61850 Interoperability
472
The IEC 61850 Data Model
472
Figure 208: Data Model Layers in IEC61850
472
IEC 61850 in Micom Ieds
473
IEC 61850 Data Model Implementation
473
IEC 61850 Communication Services Implementation
473
IEC 61850 Peer-To-Peer (GOOSE) Communications
474
Mapping GOOSE Messages to Virtual Inputs
474
Ethernet Functionality
474
IEC 61850 Configuration
474
Read Only Mode
476
Courier Protocol Blocking
476
IEC 61850 Protocol Blocking
477
Read-Only Settings
477
Read-Only DDB Signals
477
Time Synchronisation
478
Demodulated IRIG-B
478
Figure 209: GPS Satellite Timing Signal
478
IRIG-B Implementation
479
Sntp
479
Loss of SNTP Server Signal Alarm
479
IEEE 1588 Precision Time Protocol
479
Accuracy and Delay Calculation
479
PTP Domains
480
Time Synchronsiation Using the Communication Protocols
480
Figure 210: Timing Error Using Ring or Line Topology
480
Chapter 19 Cyber-Security
481
Overview
483
The Need for Cyber-Security
484
Standards
485
NERC Compliance
485
Cip 002
486
Cip 007
487
Ieee 1686-2007
487
Cyber-Security Implementation
489
NERC-Compliant Display
489
Four-Level Access
490
Figure 211: Default Display Navigation
490
Blank Passwords
491
Password Rules
491
Access Level Ddbs
492
Enhanced Password Security
492
Password Strengthening
492
Password Validation
492
Password Blocking
493
Password Recovery
494
Password Encryption
495
Disabling Physical Ports
495
Disabling Logical Ports
495
Security Events Management
496
Logging out
498
Chapter 20 Installation
499
Chapter Overview
501
Handling the Goods
502
Receipt of the Goods
502
Unpacking the Goods
502
Storing the Goods
502
Dismantling the Goods
502
Mounting the Device
503
Flush Panel Mounting
503
Figure 212: Location of Battery Isolation Strip
503
Rack Mounting
504
Figure 213: Rack Mounting of Products
504
Cables and Connectors
506
Terminal Blocks
506
Figure 214: Terminal Block Types
506
Power Supply Connections
507
Earth Connnection
507
Current Transformers
507
Voltage Transformer Connections
508
Watchdog Connections
508
EIA(RS)485 and K-Bus Connections
508
IRIG-B Connection
508
Opto-Input Connections
508
Output Relay Connections
508
Ethernet Metallic Connections
509
Ethernet Fibre Connections
509
RS232 Connection
509
Download/Monitor Port
509
GPS Fibre Connection
509
Fibre Communication Connections
509
Case Dimensions
510
Case Dimensions 40TE
510
Figure 215: 40TE Case Dimensions
510
Case Dimensions 60TE
511
Figure 216: 60TE Case Dimensions
511
Case Dimensions 80TE
512
Figure 217: 80TE Case Dimensions
512
Chapter 21 Commissioning Instructions
513
Chapter Overview
515
General Guidelines
516
Commissioning Test Menu
517
Opto I/P Status Cell (Opto-Input Status)
517
Relay O/P Status Cell (Relay Output Status)
517
Test Port Status Cell
517
Monitor Bit 1 to 8 Cells
517
Test Mode Cell
518
Test Pattern Cell
518
Contact Test Cell
518
Test Leds Cell
518
Test Autoreclose Cell
518
Red and Green LED Status Cells
519
Using a Monitor Port Test Box
519
Commissioning Equipment
520
Recommended Commissioning Equipment
520
Essential Commissioning Equipment
520
Advisory Test Equipment
521
Product Checks
522
Product Checks with the IED De-Energised
522
Visual Inspection
523
Current Transformer Shorting Contacts
523
Insulation
523
External Wiring
523
Watchdog Contacts
524
Power Supply
524
Product Checks with the IED Energised
524
Test LCD
525
Date and Time
525
Test Leds
526
Test Alarm and Out-Of-Service Leds
526
Test Trip LED
526
Test User-Programmable Leds
526
Test Opto-Inputs
526
Test Output Relays
526
Test Serial Communication Port RP1
527
Figure 218: RP1 Physical Connection
527
Test Serial Communication Port RP2
528
Test Ethernet Communication
528
Figure 219: Remote Communication Using K-Bus
528
Secondary Injection Tests
529
Test Current Inputs
529
Test Voltage Inputs
529
Setting Checks
531
Apply Application-Specific Settings
531
Transferring Settings from a Settings File
531
Entering Settings Using the HMI
531
Protection Timing Checks
533
Overcurrent Check
533
Connecting the Test Circuit
533
Performing the Test
533
Check the Operating Time
533
Onload Checks
535
Confirm Current Connections
535
Confirm Voltage Connections
535
On-Load Directional Test
536
Final Checks
537
Chapter 22 Maintenance and Troubleshooting
539
Chapter Overview
541
Maintenance
542
Maintenance Checks
542
Alarms
542
Opto-Isolators
542
Output Relays
542
Measurement Accuracy
542
Replacing the Device
543
Repairing the Device
544
Removing the Front Panel
544
Figure 220: Possible Terminal Block Types
544
Replacing Pcbs
545
Replacing the Main Processor Board
545
Replacement of Communications Boards
546
Figure 221: Front Panel Assembly
546
Replacement of the Input Module
547
Replacement of the Power Supply Board
547
Replacement of the I/O Boards
548
Recalibration
548
Changing the Battery
548
Post Modification Tests
549
Battery Disposal
549
Cleaning
549
Troubleshooting
550
Self-Diagnostic Software
550
Power-Up Errors
550
Error Message or Code on Power-Up
550
Out of Service LED on at Power-Up
551
Error Code During Operation
552
Backup Battery
552
Mal-Operation During Testing
552
Failure of Output Contacts
552
Failure of Opto-Inputs
552
Incorrect Analogue Signals
553
PSL Editor Troubleshooting
553
Diagram Reconstruction
553
PSL Version Check
553
Repair and Modification Procedure
554
Chapter 23 Technical Specifications
555
Chapter Overview
557
Interfaces
558
Front Serial Port
558
Download/Monitor Port
558
Rear Serial Port
558
Fibre Rear Serial Port
558
Optional Rear Serial Port (SK5)
559
IRIG-B (Demodulated)
559
IRIG-B (Modulated)
559
Rear Serial Port 2
559
Rear Ethernet Port Copper
560
Rear Ethernet Port Fibre
560
100 Base Fx Receiver Characteristics
560
100 Base Fx Transmitter Characteristics
561
Performance of Current Protection Functions
562
Transient Overreach and Overshoot
562
Phase Overcurrent Protection
562
Phase Overcurrent Directional Parameters
562
Voltage Dependent Overcurrent Protection
562
Earth Fault Protection
563
Earth Fault Directional Parameters
563
Sensitive Earth Fault Protection
564
SEF Directional Parameters
564
Restricted Earth Fault Protection
564
Negative Sequence Overcurrent Protection
565
NPSOC Directional Parameters
565
Circuit Breaker Fail and Undercurrent Protection
565
Broken Conductor Protection
565
Thermal Overload Protection
565
Cold Load Pickup Protection
566
Selective Overcurrent Protection
566
Voltage Dependent Overcurrent Protection
566
Neutral Admittance Protection
566
Performance of Voltage Protection Functions
567
Undervoltage Protection
567
Overvoltage Protection
567
Residual Overvoltage Protection
567
Negative Sequence Voltage Protection
567
Rate of Change of Voltage Protection
568
Performance of Frequency Protection Functions
569
Basic Overfrequency Protection
569
Basic Underfrequency Protection
569
Advanced Overfrequency Protection
569
Advanced Underfrequency Protection
570
Supervised Rate of Change of Frequency Protection
570
Independent Rate of Change of Frequency Protection
570
Average Rate of Change of Frequency Protection
571
Load Restoration
571
Power Protection Functions
572
Overpower / Underpower Protection
572
Sensitive Power Protection
572
Performance of Monitoring and Control Functions
573
Voltage Transformer Supervision
573
Standard Current Transformer Supervision
573
CB State and Condition Monitoring
573
PSL Timers
573
Measurements and Recording
574
General
574
Disturbance Records
574
Event, Fault and Maintenance Records
574
Fault Locator
574
Ratings
575
AC Measuring Inputs
575
Current Transformer Inputs
575
Voltage Transformer Inputs
575
Auxiliary Supply Voltage
575
Nominal Burden
576
Power Supply Interruption
576
Battery Backup
577
Input / Output Connections
578
Isolated Digital Inputs
578
Nominal Pickup and Reset Thresholds
578
Standard Output Contacts
578
High Break Output Contacts
579
Watchdog Contacts
579
Mechanical Specifications
580
Physical Parameters
580
Enclosure Protection
580
Mechanical Robustness
580
Transit Packaging Performance
580
Type Tests
581
Insulation
581
Creepage Distances and Clearances
581
High Voltage (Dielectric) Withstand
581
Impulse Voltage Withstand Test
581
Environmental Conditions
582
Ambient Temperature Range
582
Temperature Endurance Test
582
Ambient Humidity Range
582
Corrosive Environments
582
Electromagnetic Compatibility
583
Mhz Burst High Frequency Disturbance Test
583
Damped Oscillatory Test
583
Immunity to Electrostatic Discharge
583
Electrical Fast Transient or Burst Requirements
583
Surge Withstand Capability
583
Surge Immunity Test
584
Immunity to Radiated Electromagnetic Energy
584
Radiated Immunity from Digital Communications
584
Radiated Immunity from Digital Radio Telephones
584
Immunity to Conducted Disturbances Induced by Radio Frequency Fields
584
Magnetic Field Immunity
585
Conducted Emissions
585
Radiated Emissions
585
Power Frequency
585
Regulatory Compliance
586
EMC Compliance: 2014/30/EU
586
LVD Compliance: 2014/35/EU
586
R&TTE Compliance: 2014/53/EU
586
UL/CUL Compliance
586
ATEX Compliance: 2014/34/EU
586
Appendix A Ordering Options
589
Appendix B Settings and Signals
591
Appendix C Wiring Diagrams
599
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