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NEC uPD78082 manual available for free PDF download: User Manual
NEC uPD78082 User Manual (274 pages)
8-BIT SINGLE-CHIP MICROCONTROLLER
Brand:
NEC
| Category:
Computer Hardware
| Size: 1.44 MB
Table of Contents
Table of Contents
12
Chapter 1 Outline
24
Features
24
Applications
25
Ordering Information
25
Quality Grade
26
Pin Configuration (Top View)
27
Series Development
32
Block Diagram
34
Outline of Function
35
Differences between the PD78081, 78082 and 78P083, the PD78081(A), 78082(A) and 78P083(A), and the PD78081(A2)
36
Chapter 2 Pin Function
38
Pin Function List
38
Normal Operating Mode Pins
38
PROM Programming Mode Pins ( PD78P083 Only)
39
Description of Pin Functions
40
P00 to P03 (Port 0)
40
P10 to P17 (Port 1)
40
P30 to P37 (Port 3)
41
P50 to P57 (Port 5)
41
P70 to P72 (Port 7)
42
P100 to P101 (Port 10)
42
Av Ref
43
Av DD
43
Av Ss
43
Reset
43
X1 and X2
43
VDD
43
Vss
43
PP ( PD78P083 Only)
43
IC (Mask ROM Version Only)
44
NC (44-Pin Plastic QFP Versions Only)
44
Pin Input/Output Circuits and Recommended Connection of Unused Pins
45
Type of Input/Output Circuit of each Pin
45
Pin Input/Output Circuit of List
46
Chapter 3 Cpu Architecture
48
Memory Spaces
48
Memory Map ( PD78081)
48
Memory Map ( PD78082)
49
Memory Map ( PD78P083)
50
Internal Program Memory Space
51
Vector Table
51
Data Memory Addressing
52
Internal Data Memory Space
52
Special Function Register (SFR) Area
52
Data Memory Addressing ( PD78081)
53
Data Memory Addressing ( PD78082)
54
Data Memory Addressing ( PD78P083)
55
Processor Registers
56
Control Registers
56
Program Counter Configuration
56
Program Status Word Configuration
56
Data to be Reset from Stack Memory
58
General Registers
59
Data to be Saved to Stack Memory
58
Stack Pointer Configuration
58
General Register Configuration
59
Special Function Register (SFR)
60
Special-Function Register List (1/2)
61
Special-Function Register List (2/2)
62
Instruction Address Addressing
63
Relative Addressing
63
Immediate Addressing
64
Table Indirect Addressing
65
Register Addressing
66
Operand Address Addressing
67
Implied Addressing
67
Register Addressing
68
Direct Addressing
69
Short Direct Addressing
70
Special-Function Register (SFR) Addressing
72
Register Indirect Addressing
73
Based Addressing
74
Based Indexed Addressing
75
Stack Addressing
75
Chapter 4 Port Functions
76
Port Functions
76
Port Types
76
Port Functions
77
Port Configuration
78
Port 0
78
P00 Block Diagram
79
P01 to P03 Block Diagram
79
P10 to P17 Block Diagram
80
Port
81
Port 1
80
P30 to P37 Block Diagram
81
Port
82
P50 to P57 Block Diagram
82
Port
83
P70 Block Diagram
83
P71 and P72 Block Diagram
84
Port
85
Port 10
85
P100 to P101 Block Diagram
85
Port Function Control Registers
86
Port Mode Register and Output Latch Settings When Using Dual-Fucntions
87
Port Mode Register Format
88
Pull-Up Resistor Option Register Format
89
Port Function Operations
90
Writing to Input/Output Port
90
Reading from Input/Output Port
90
Operations on Input/Output Port
90
Chapter 5 Clock Generator
92
Clock Generator Functions
92
Clock Generator Configuration
92
Block Diagram of Clock Generator
93
Clock Generator Control Register
94
Processor Clock Control Register Format
94
Oscillation Mode Selection Register Format
95
System Clock Oscillator
96
External Circuit of Main System Clock Oscillator
96
Main System Clock Oscillator
96
Examples of Oscillator with Bad Connection (1/2)
97
Scaler
98
Clock Generator Operations
99
Changing CPU Clock Settings
100
Time Required for CPU Clock Switchover
100
Maximum Time Required for CPU Clock Switchover
100
CPU Clock Switching Procedure
101
CPU Clock Switching
101
Chapter 6 8-Bit Timer/Event Counters 5 and 6
102
Timer/Event Counter Types and Functions
102
8-Bit Timer/Event Counters 5 and 6 Functions
103
8-Bit Timer/Event Counters 5 and 6 Interval Times
103
8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
104
8-Bit Timer/Event Counters 5 and 6 Configurations
105
8-Bit Timer/Event Counters 5 and 6 Block Diagram
105
Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
106
8-Bit Timer/Event Counters 5 and 6 Control Registers
107
Timer Clock Select Register 5 Format
108
Timer Clock Select Register 6 Format
109
8-Bit Timer Mode Control Register 5 Format
110
8-Bit Timer Mode Control Register 6 Format
111
Port Mode Register 10 Format
112
8-Bit Timer/Event Counters 5 and 6 Operations
113
8-Bit Timer Mode Control Register Settings for Interval Timer Operation
113
Interval Timer Operations
113
Interval Timer Operation Timings
114
8-Bit Timer/Event Counters 5 and 6 Interval Times
115
External Event Counter Operation
116
Square-Wave Output
117
8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
118
PWM Output Operations
119
Bit Timer Mode Control Register Settings for PWM Output Operation
119
PWM Output Operation Timing (Active High Setting)
120
PWM Output Operation Timings (Crn0 = 00H, Active High Setting)
120
PWM Output Operation Timings (Crn0 = FFH, Active High Setting)
121
Cautions on 8-Bit Timer/Event Counters 5 and 6
123
Bit Timer Registers 5 and 6 Start Timing
123
External Event Counter Operation Timing
123
Timing after Compare Register Change During Timer Count Operation
124
Chapter 7 Watchdog Timer
126
Watchdog Timer Functions
126
Watchdog Timer Overrun Detection Times
126
Interval Times
127
Watchdog Timer Configuration
128
Watchdog Timer Block Diagram
128
Watchdog Timer Control Registers
129
Timer Clock Select Register 2 Format
130
Watchdog Timer Mode Register Format
131
Watchdog Timer Operations
132
Watchdog Timer Operation
132
Watchdog Timer Overrun Detection Time
132
Interval Timer Operation
133
Interval Timer Interval Time
133
Chapter 8 Clock Output Control Circuit
134
Clock Output Control Circuit Functions
134
Remote Controlled Output Application Example
134
Clock Output Control Circuit Configuration
135
Clock Output Control Circuit Block Diagram
135
Clock Output Function Control Registers
136
Timer Clock Select Register 0 Format
136
Port Mode Register 3 Format
137
Chapter 9 Buzzer Output Control Circuit
138
Buzzer Output Control Circuit Functions
138
Buzzer Output Control Circuit Configuration
138
Buzzer Output Control Circuit Block Diagram
138
Buzzer Output Function Control Registers
139
Timer Clock Select Register 2 Format
140
Port Mode Register 3 Format
141
Chapter 10 A/D Converter
142
A/D Converter Functions
142
A/D Converter Configuration
142
A/D Converter Block Diagram
143
A/D Converter Control Registers
145
A/D Converter Mode Register Format
146
A/D Converter Input Select Register Format
147
External Interrupt Mode Register 1 Format
148
A/D Converter Operations
149
Basic Operations of A/D Converter
149
A/D Converter Basic Operation
150
Input Voltage and Conversion Results
151
Relations between Analog Input Voltage and A/D Conversion Result
151
A/D Converter Operating Mode
152
A/D Conversion by Hardware Start
152
A/D Conversion by Software Start
153
A/D Converter Cautions
154
Example of Method of Reducing Current Dissipation in Standby Mode
154
Analog Input Pin Disposition
155
Chapter 11 Serial Interface Channel 2
158
Serial Interface Channel 2 Functions
158
Serial Interface Channel 2 Configuration
159
Serial Interface Channel 2 Block Diagram
160
Baud Rate Generator Block Diagram
161
Serial Interface Channel 2 Control Registers
163
Serial Operating Mode Register 2 Format
163
Asynchronous Serial Interface Mode Register Format
164
Serial Interface Channel 2 Operating Mode Settings
165
Asynchronous Serial Interface Status Register Format
166
Baud Rate Generator Control Register Format (1/2)
167
Baud Rate Generator Control Register Format (2/2)
168
Relation between Main System Clock and Baud Rate
169
Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
170
Serial Interface Channel 2 Operation
171
Operation Stop Mode
171
Asynchronous Serial Interface (UART) Mode
173
Relation between Main System Clock and Baud Rate
178
Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
179
Asynchronous Serial Interface Transmit/Receive Data Format
180
Asynchronous Serial Interface Transmission Completion Interrupt Request Timing
182
Asynchronous Serial Interface Reception Completion Interrupt Request Timing
183
Receive Error Causes
184
Receive Error Timing
184
3-Wire Serial I/O Mode
186
Wire Serial I/O Mode Timing
191
Circuit of Switching in Transfer Bit Order
192
Chapter 12 Interrupt Function
194
Interrupt Function Types
194
Interrupt Sources and Configuration
195
Interrupt Source List
195
Basic Configuration of Interrupt Function (1/2)
196
Basic Configuration of Interrupt Function (2/2)
197
Interrupt Function Control Registers
198
Various Flags Corresponding to Interrupt Request Sources
198
Interrupt Request Flag Register Format
199
Interrupt Mask Flag Register Format
200
Priority Specify Flag Register Format
201
External Interrupt Mode Register 0 Format
202
External Interrupt Mode Register 1 Format
202
Program Status Word Configuration
203
Interrupt Servicing Operations
204
Non-Maskable Interrupt Request Acknowledge Operation
204
Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment
205
Non-Maskable Interrupt Request Acknowledge Timing
205
Non-Maskable Interrupt Request Acknowledge Operation
206
Maskable Interrupt Request Acknowledge Operation
207
Times from Maskable Interrupt Request Generation to Interrupt Service
207
Interrupt Request Acknowledge Processing Algorithm
208
Interrupt Request Acknowledge Timing (Maximum Time)
209
Multiple Interrupt Servicing
210
Software Interrupt Request Acknowledge Operation
210
Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
211
Interrupt Request Reserve
214
Interrupt Request Hold
215
Chapter 13 Standby Function
216
Standby Function and Configuration
216
Standby Function
216
Standby Function Control Register
217
Oscillation Stabilization Time Select Register Format
217
Standby Function Operations
218
HALT Mode
218
HALT Mode Operating Status
218
HALT Mode Clear Upon Interrupt Generation
219
Operation after HALT Mode Release
220
HALT Mode Release by RESET Input
220
STOP Mode
221
STOP Mode Operating Status
221
STOP Mode Release by Interrupt Generation
222
Operation after STOP Mode Release
223
Release by STOP Mode RESET Input
223
Chapter 14 Reset Function
224
Reset Function
224
Block Diagram of Reset Function
224
Timing of Reset Input by RESET Input
225
Timing of Reset Due to Watchdog Timer Overflow
225
Timing of Reset Input in STOP Mode by RESET Input
225
Chapter 15 Pd78P083
228
Differences between the PD78P083 and Mask ROM Versions
228
Memory Size Switching Register
229
Examples of Memory Size Switching Register Settings
229
Memory Size Switching Register Format
229
PROM Programming
230
Operating Modes
230
PROM Programming Operating Modes
230
PROM Write Procedure
232
Page Program Mode Flowchart
232
Page Program Mode Timing
233
Byte Program Mode Flowchart
234
Byte Program Mode Timing
235
PROM Reading Procedure
236
Erasure Procedure ( PD78P083DU Only)
237
Opaque Film Masking the Window ( PD78P083DU Only)
237
Screening of One-Time PROM Versions
237
Chapter 16 Instruction Set
238
Legends Used in Operation List
239
Operand Identifiers and Description Methods
239
Description of "Operation" Column
240
Description of "Flag Operation" Column
240
Operation List
241
Instructions Listed by Addressing Type
249
Appendix A Development Tools
254
Language Processing Software
256
PROM Programming Tools
257
Hardware
257
Software
257
A.2.1 Hardware
257
A.2.2 Software
257
Debugging Tools
258
Hardware
258
A.3 Debugging Tools
258
A.3.1 Hardware
258
Software (1/3)
259
A.3.2 Software (1/3)
259
Software (2/3)
260
A.3.2 Software (2/3)
260
Software (3/3)
261
A.3.2 Software (3/3)
261
OS for IBM PC
262
System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator
263
Appendix B Embedded Software
266
Real-Time os
267
B.1 Real-Time os
267
Fuzzy Inference Development Support System
268
Appendix C Register Index
270
Register Index
270
Appendix D Revision History
272
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