Samsung S3F84B8 IH Cooker Manuals

Manuals and User Guides for Samsung S3F84B8 IH Cooker. We have 2 Samsung S3F84B8 IH Cooker manuals available for free PDF download: User Manual, Design Manual

Samsung S3F84B8 User Manual (323 pages)

8-bit CMOS

Brand: Samsung | Category: Microcontrollers | Size: 1.49 MB

Overview of S3F84B8 Microcontroller
18
Key Features of S3F84B8
19
Block Diagram of S3F84B8
22
Pin Assignments
23
Pin Descriptions
24
Table 1-2 Pin Descriptions Used to Read/Write the Flash ROM
25
Pin Circuits
26
Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)
27
Address Spaces
31
Internal Program Memory (ROM)
32
Smart Option
33
Register Architecture
34
Figure 2-3 Internal Register File Organization in S3F84B8
35
Register Page Pointer (PP)
36
Register Set 1
37
Prime Register Space
38
Working Registers
39
Using the Register Points (RP)
40
Figure 2-8 Non-Contiguous 16 Byte Working Register Block
41
Register Addressing
42
Common Working Register Area (C0H–CFH)
44
Bit Working Register Addressing
45
Figure 2-13 4-Bit Working Register Addressing Example
46
Bit Working Register Addressing
47
Figure 2-15 8-Bit Working Register Addressing Example
48
System and User Stack
49
Addressing Modes
51
Register (R) Addressing Mode
52
Indirect Register (IR) Addressing Mode
53
Indirect Register (IR) Addressing Mode (Continued)
54
Indirect Register (IR) Addressing Mode (Continued)
55
Indirect Register (IR) Addressing Mode (Concluded)
56
Indexed (X) Addressing Mode
57
Indexed (X) Addressing Mode (Continued)
58
Indexed (X) Addressing Mode (Concluded)
59
Direct Address (DA) Mode
60
Direct Address (DA) Mode (Continued)
61
Indirect Address (IA) Mode
62
Relative Address (RA) Mode
63
Immediate Mode (IM)
64
Control Registers
65
ADCON — A/D Converter Control Register: FAH, BANK0
69
AMTDATA — Anti-Mis-Trigger Data Register: F6H, BANK0
70
BUZCON — BUZ Control Register: F7H, BANK0
71
CLKCON — Clock Control Register: D4H, BANK0
72
CMP0CON — Comparator0 Control Register: EAH, BANK0
73
CMP1CON — Comparator1 Control Register: EBH, BANK0
74
CMP2CON — Comparator1 Control Register: ECH, BANK0
75
CMP3CON — Comparator1 Control Register: EDH, BANK0
76
CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0
77
FLAGS — System Flags Register: D5H, BANK0
78
FMCON — Flash Memory Control Register: F5H, BANK1
79
FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK1
80
IMR — Interrupt Mask Register: DDH, BANK0
81
IPH — Instruction Pointer (High Byte): DAH, BANK0
82
IPR — Interrupt Priority Register: FFH, BANK0
83
IRQ — Interrupt Request Register: DCH, BANK0
84
OPACON — OP AMP Control Register: E0H, BANK1
85
P0CONH — Port 0 Control Register (High Byte): E4H, Bank0
86
P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0
87
P0INT — Port 0 Interrupt Control Register: E3H, BANK0
88
P0PND — Port 0 Interrupt Pending Register: E6H, BANK0
89
P1CON — Port 1 Control Register: E7H, BANK0
90
P2CONH — Port 2 Control Register (High Byte): E8H, BANK0
91
P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0
92
PWMCON — PWM Control Register: EFH, BANK0
93
PWMCCON — PWM CMP Control Register: F0H, BANK0
94
PWMDL — Comparator0 Output Delay Register: F5H, Bank0
95
RESETID — Reset Source Indicating Register: F2H, BANK1
96
RP0 — Register Pointer 0: D6H, BANK0
97
SPL — Stack Pointer: D9H, BANK0
98
SYM — System Mode Register: DEH, BANK0
99
TACON — Timer a Control Register: E1H, BANK1
100
TAPS — TA Pre-Scalar Register: E2H, BANK1
101
TCCON — Timer C Control Register: E5H, BANK1
102
TCPS — TC Pre-Scalar Register: E6H, BANK1
103
TDCON — Timer D Control Register: E9H, BANK1
104
TDPS — TD Pre-Scalar Register: EAH, BANK1
105
Interrupt Structure
106
Interrupt Types
107
S3F84B8 Interrupt Structure
108
Interrupt Vector Addresses
109
System-Level Interrupt Control Registers
110
Interrupt Processing Control Points
111
Peripheral Interrupt Control Registers
112
System Mode Register (SYM)
113
Interrupt Mask Register (IMR)
114
Interrupt Priority Register (IPR)
115
Interrupt Request Register (IRQ)
117
Interrupt Pending Function Types
118
Interrupt Source Polling Sequence
119
Generating Interrupt Vector Addresses
120
Instruction Pointer (IP)
121
Procedure for Initiating Fast Interrupts
122
Instruction Set
123
Flags Register (FLAGS)
127
Flag Descriptions
128
Instruction Set Notation
129
Table 6-4 Instruction Notation Conventions
130
Table 6-5 Opcode Quick Reference
131
Condition Codes
133
Instruction Descriptions
134
ADC — Add with Carry
135
ADD — Add
136
AND — Logical and
137
BAND — Bit and
138
BCP — Bit Compare
139
BITC — Bit Complement
140
BITR — Bit Reset
141
BITS — Bit Set
142
BOR — Bit or
143
BTJRF — Bit Test, Jump Relative on False
144
BTJRT — Bit Test, Jump Relative on True
145
BXOR — Bit XOR
146
CALL — Call Procedure
147
CCF — Complement Carry Flag
148
CLR — Clear
149
COM — Complement
150
CP — Compare
151
CPIJE — Compare, Increment, and Jump on Equal
152
CPIJNE — Compare, Increment, and Jump on Non-Equal
153
DA — Decimal Adjust
154
DA — Decimal Adjust (Continued)
155
DEC — Decrement
156
DECW — Decrement Word
157
DI — Disable Interrupts
158
DIV — Divide (Unsigned)
159
DJNZ — Decrement and Jump if Non-Zero
160
EI — Enable Interrupts
161
ENTER — Enter
162
Figure 6-3 Example of the Usage of EXIT Statement
163
IDLE — Idle Operation
164
INC — Increment
165
INCW — Increment Word
166
IRET — Interrupt Return
167
JP — Jump
168
JR — Jump Relative
169
LD — Load
170
LD — Load (Continued)
171
LDB — Load Bit
172
LDC/LDE — Load Memory
173
LDC/LDE — Load Memory (Continued)
174
LDCD/LDED — Load Memory and Decrement
175
LDCI/LDEI — Load Memory and Increment
176
LDCPD/LDEPD — Load Memory with Pre-Decrement
177
LDCPI/LDEPI — Load Memory with Pre-Increment
178
LDW — Load Word
179
MULT — Multiply (Unsigned)
180
NEXT — Next
181
NOP — no Operation
182
OR — Logical or
183
POP — Pop from Stack
184
POPUD — Pop User Stack (Decrementing)
185
POPUI — Pop User Stack (Incrementing)
186
PUSH — Push to Stack
187
PUSHUD — Push User Stack (Decrementing)
188
PUSHUI — Push User Stack (Incrementing)
189
RCF — Reset Carry Flag
190
RET — Return
191
RL — Rotate Left
192
RLC — Rotate Left through Carry
193
RR — Rotate Right
194
RRC — Rotate Right through Carry
195
SB0 — Select Bank 0
196
SBC — Subtract with Carry
197
SCF — Set Carry Flag
198
SRA — Shift Right Arithmetic
199
RP/SRP0/SRP1 — Set Register Pointer
200
STOP — Stop Operation
201
SUB — Subtract
202
SWAP — Swap Nibbles
203
TCM — Test Complement under Mask
204
TM — Test under Mask
205
WFI — Wait for Interrupt
206
XOR — Logical Exclusive or
207
Clock Circuit
208
Clock Status During Power-Down Modes
209
Reset and Power-Down
211
MCU Initialization Sequence
213
Power-Down Modes
214
Idle Mode
215
Hardware Reset Values
216
I/O Port
219
Port 0
220
Figure 9-1 Port 0 Control Register High Byte (P0CONH)
221
Figure 9-2 Port 0 Control Register Low Byte (P0CONL)
222
Figure 9-3 Port 0 Interrupt Control Register (P0INT)
223
Figure 9-4 Port 0 Interrupt Pending Register (P0PND)
224
Port 1
225
Port 2
227
Figure 9-6 Port 2 High-Byte Control Register (P2CONH)
228
Figure 9-7 Port 2 Low-Byte Control Register (P2CONL)
229
Basic Timer
230
Basic Timer Control Register (BTCON)
231
Basic Timer Function Description
232
Figure 10-2 Oscillation Stabilization Time on RESET
233
Figure 10-3 Oscillation Stabilization Time on STOP Mode Release
234
Bit Timer a
236
Functional Description
237
Timer a Control Register (TACON)
238
Block Diagram of Timer a
241
Timer
242
Functional Description of One 16-Bit Timer Mode (Timer 0)
243
Block Diagram of Timer 0
245
Two 8-Bit Timers Mode (Timer C and D)
246
Figure 12-5 Timer C Prescaler Register (TCPS)
248
Functional Description of Two 8-Bit Timers Mode (Timer C and D)
250
Figure 12-8 Timers C and D Function Block Diagram
251
Pulse Width Modulation Mode (Timer D)
252
A/D Converter
253
Using A/D Pins for Standard Digital Input
254
Internal Reference Voltage Levels
255
Conversion Timing
257
Comparator
259
Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)
260
Comparator 1/2/3
262
Figure 14-7 CMP Interrupt Mode Control Register (CMPINT)
264
Operational Amplifier
266
OPAMP Control Register
267
Reference Circuit
268
Bit Ih-Pwm
269
Functional Description of 10-Bit IH-PWM
270
PWM Functional Description
271
PWM Control Register (PWMCON)
272
PWM CMP Linkage Control Register (PWMCCON)
273
Block Diagram of PWM Module
274
Figure 16-6 Example of the Cooperation of PWM and Comparator 0_Delay Trigger
275
Programmable Buzzer
277
BUZ Frequency Table (@4Mhz)
278
Flash Mcu Rom
280
Embedded Flash Memory Interface
282
User Program Mode
283
Flash Memory Control Registers (User Program Mode)
284
Flash Memory Sector Address Registers
285
Sector Erase
286
Figure 19-7 Sector Erase Flowchart in User Program Mode
287
Programming
289
Figure 19-8 Byte Program Flowchart in a User Program Mode
290
Figure 19-9 Program Flowchart in a User Program Mode
291
Reading
295
Hard Lock Protection
296
Low Voltage Reset
297
Electrical Data
299
Table 21-1 Absolute Maximum Ratings
300
Figure 21-2 Operating Voltage Range @ External Clock
305
Figure 21-4 Stop Mode Release Timing When Initiated by a RESET
306
Table 21-7 A/D Converter Electrical Characteristics
307
Table 21-8 OP AMP Electrical Characteristics
308
Table 21-11 Flash Memory AC Electrical Characteristics
309
Figure 21-6 Circuit Diagram to Improve the EFT Characteristics
310
Development Tools
311
Development System Configuration
312
TB84B8 Target Board
313
Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package
317
Third Parties for Development Tools
318
OTP/MTP Programmer (Writer)
319
Mechanical Data
321

Samsung S3F84B8 Design Manual (25 pages)

All-in-One IH Cooker

Brand: Samsung | Category: Kitchen Appliances | Size: 0.41 MB

Table of Contents
4
1 Overview of Ih Cooker (Ihc)

7
- Induction Cooking Principle
  7
  - How Induction Cooking Works
    7
  - Figure 1-1 How IH Cooker Works
    7
- Key Features of S3F84B8
  8
- System Principle
  9
  - Heating
    9
  - Protection
    9
2 Hardware Implementation

10
- System Diagram and Pin Assignment
  10
- Figure 2-1 Block Diagram of IH Cooker System
  10
- Table 2-1 S3F84B8 Pin Assignment in IH Cooker System
  11
- Power Supply
  12
- Synchronization Circuit
  13
- Figure 2-4 Waveform of the Synchronization Circuit
  14
- Power Control
  15
- System Protection
  17
- Other Functions
  19
  - Pan Detection
    19
  - Buzzer and Fan Control
    19
  - Figure 2-8 Buzzer and Fan Control
    19
  - Key and Display Circuit
    20
3 Software Implementation

21
4 Appendix

25
- Error Code
  25
- Schmatic
  25
- Source Code
  25

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Samsung S3F84B8 IH Cooker Manuals

Samsung S3F84B8 User Manual (323 pages)

Table of Contents

Samsung S3F84B8 Design Manual (25 pages)

Table of Contents

1 Overview of Ih Cooker (Ihc)

2 Hardware Implementation

3 Software Implementation

4 Appendix

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