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System Module
Figure 97 System start-up timing
Clocking scheme
In BB5.0, two main clocks are provided to the system: 38.4MHz RF clock produced by VCTCXO in RF section and
32.768kHz sleep clock produced by RETU with an external crystal.
RF clock is generated only when VCTCXO is powered on by RETU regulator. Regulator itself is activated by SleepX
signals from both RAP3G and Helen3. When both CPUs are on sleep, RF clock is stopped.
RF clock is used by RAP3G that then provides (divided) 19.2MHz SysClk further to OMAP. Both RAPG and Helen3
have internal PLLs which then create clock signals for other peripheral devices/interfaces like RS MMC, SIM, CCP,
I2C and memories.
32k Sleep Clock is always powered on after startup. Sleep clock is used by RAP3G and OMAP for low-power
operation.
SMPS Clk is 2.4MHz clock line from RAP3G to Tahvo used for switch mode regulator synchronizing in active
mode. In deep sleep mode, when VCTCXO is off, this signal is set to '0'-state.
BT Clk is 38.4MHz signal from Hinku ASIC to BT module.
CLK600 is 600KHz signal from Tahvo to APE VCORE SMPS. The clock source is internal RC oscillator in Tahvo (during
the power-up sequence) or RAP3G SMPS Clk divided by 4 after the power-up sequence.
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