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3 7 63 1515 0
Pin No.
Pin Name
57
NO USE
58
LAT2
59, 60
NO USE
61
SHIFT
62
SCDT
63
SOFT_MUTE
64
INT
65
LAT1
66
TUNED
67
TUNER LED
68
OVF
69
LAT3
70, 71
VOLB, VOLA
72
FL_DIN
73
FL_CLK
74
FL_STB
75, 76
NO USE
77
RSTX
78
OVFW
79, 80
X1A, X0A
VSS
81
TE
L 13942296513
82
X0
83
X1
84
VCC3
85
T.CLK
86
T.DATA
87
SLATCH
88
T_DO
89
T_MUTE
90
ST
91
NO USE
92
LRCK_SW
93
XMODE
94
CKSEL1
95
CLK
96
CE
97
DI
98
DO
99
ERROR
100
XSTATE
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I/O
-
Not used
O
Latch control signal output to the stream processor
-
Not used
O
Shift clock signal output to the stream processor
O
Serial data output to the stream processor
O
Soft muting on/off control signal output to the stream processor "L": muting on
O
Reset signal output to the stream processor "L": reset
O
Latch control signal output to the stream processor
I
Tuning detection signal input from the tuner "L": tuned
O
LED drive signal output of the tuner indicator "L": LED on
I
Over flow status input from the stream processor (front/surround/center)
O
Latch control signal output to the stream processor
I
Jog dial pulse input from the rotary encoder (for MASTER VOLUME)
O
Serial data output to the fluorescent indicator tube
O
Serial data transfer clock signal output to the fluorescent indicator tube
O
Strobe signal output to the fluorescent indicator tube
-
Not used
System reset signal input terminal "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
I
Over flow status input from the stream processor (sub woofer)
-
Not used
-
Ground terminal
I
System clock input terminal (24 MHz)
O
System clock output terminal (24 MHz)
-
Power supply terminal (+3.3V)
O
PLL serial data transfer clock signal output to the tuner
O
PLL serial data output to the tuner
O
Latch control signal output to the tuner
I
PLL serial data input from the tuner
O
Tuner muting on/off control signal output to the tuner
I
FM stereo detection signal input from the tuner
-
Not used
O
Signal switch signal output terminal Not used
O
System reset signal output to the digital audio interface receiver "L": reset
O
Output clock selection signal output to the digital audio interface receiver
O
Serial data transfer clock signal output to the digital audio interface receiver
O
Chip enable signal output to the digital audio interface receiver
O
Serial data output to the digital audio interface receiver
I
Serial data input from the digital audio interface receiver
I
PLL lock error signal and data error flag input from the digital audio interface receiver
I
Source clock selection monitor input from the digital audio interface receiver
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u163
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2 9
8
Description
Q Q
3
6 7
1 3
1 5
co
.
STR-KS1000
9 4
2 8
0 5
8
2 9
9 4
2 8
m
Ver. 1.2
9 9
9 9
41
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