GE c60 Instruction Manual page 262
Breaker protection system
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SYSTEM SETUP
UR firmware versions 7.0 and above have a 90-5 based R-SV implementation equivalent in structure and configuration to
that of the existing IEEE C37.118 implementation of firmware version 6.0, that is, synchrophasor data at rates up to 60 Hz
for metering and 120 Hz for protection class synchrophasors. The following two figures depict the general data flow for the
generation of synchrophasor data for IEC 61850-90-5. In the first figure, when IEC 61850-90-5 is selected all real and
virtual sources are available for the IEC 61850-90-5 PMUs.
The number of PMUs and aggregators vary by product, as outlined in the table.
Table 5-16: PMU implementation by UR device
UR device
N60
C60
D60, F60, G60, L30, L90, T60
The figure shows an example of an N60 using four Logical Device PMUs (Logical Device 2 through 5) and four aggregators.
The control blocks for the aggregators are located in LD1. A 64 character LDName setting is provided.
5
Precise time input to the relay from the international time standard, via either IRIG-B or PTP, is vital for correct
synchrophasor measurement and reporting. For IRIG-B, a DC level shift IRIG-B receiver must be used for the
PMU to output proper synchrophasor values.
NOTE
Depending on the applied filter, the synchrophasors that are produced by PMUs are classified as either P (protection) or M
(Measurement) class synchrophasors. Synchrophasors available within the UR that have no filtering applied are classified
as NONE, which within the standard is classified as PRES OR UNKNOWN under the Calculation Method - ClcMth. Each
Logical Device PMU supports one MxxMMXU, MxxMSQI, PxxxMMXU , PxxxMSQI, NxxMMXU, and one NxxMSQI logical node.
5-136
Number of
Number of
PMUS
aggregators
6
4
2
2
1
1
Figure 5-64: N60 example for four logical device PMUs
Number of
Comment
analog inputs
16
1, 2, 4, or 6 PMUs can be used
16
16
C60 BREAKER PROTECTION SYSTEM – INSTRUCTION MANUAL
CHAPTER 5: SETTINGS
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