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2.2.7 POWER7 processor and intelligent energy
Energy consumption is an important area of focus for the design of the POWER7 processor,
which includes intelligent energy features that help to optimize energy usage and
performance dynamically, so that the best possible balance is maintained. Intelligent energy
features (such as EnergyScale) work with the BladeCenter Advanced Management Module
(AMM) and IBM Systems Director Active Energy Manager™ to optimize processor speed
dynamically, based on thermal conditions and system use.
For more information about the POWER7 energy management features see the following
document:
Adaptive Energy Management Features of the POWER7 Processor
http://www.research.ibm.com/people/l/lefurgy/Publications/hotchips22_power7.pdf
TurboCore mode
Note: TurboCore mode is not available on the PS703 and PS704 blades.
TurboCore mode is a feature of the POWER7 processor but is not implemented in the PS703
and PS704 servers. It uses four cores per POWER7 processor chip with access to the entire
32 MB of L3 cache (8 MB per core) and at a faster processor core frequency, which delivers
higher performance per core, and might save on software costs for those applications that are
licensed per core.
2.2.8 Comparison of the POWER7 and POWER6 processors
Table 2-2 compares characteristics of various generations of POWER7 and POWER6
processors.
Note: This shows the characteristics of the POWER7 processors in general, but not
necessarily as implemented in the POWER7 processor-based blade servers.
Implementation specifics are noted.
Table 2-2 Comparison of technology for the POWER7 processor and the prior generation
Feature
POWER7
(PS703, PS704)
Technology
45 nm
Die size
567 mm
Maximum cores
8
Maximum SMT
4 threads
threads per core
L2 Cache
256 KB per core
L3 Cache
4 MB of FLR-L3 cache
per core with each core
having access to the full
32 MB of L3 cache,
on-chip eDRAM
46
IBM BladeCenter PS703 and PS704 Technical Overview and Introduction
POWER7
(PS700, PS701, PS702)
45 nm
2
567 mm
8
4 threads
256 KB per core
4 MB of FLR-L3 cache
per core with each core
having access to the full
32 MB of L3 cache,
on-chip eDRAM
POWER6+
65 nm
2
341 mm
2
2 threads
4 MB per core
32 MB off-chip
eDRAM ASIC
POWER6
65 nm
2
2
341 mm
2
2 threads
4 MB per core
32 MB off-chip
eDRAM ASIC
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