LAD
FBD
For SCL: You must write code to replicate this function within your application.
1
Table 7- 15
P_TRIG and N_TRIG instructions
LAD / FBD
SCL
Not available
Not available
For SCL: You must write code to replicate this function within your application.
1
Table 7- 16
Data types for the parameters (P and N contacts/coils, P=, N=, P_TRIG and N_TRIG)
Parameter
Data type
M_BIT
Bool
IN
Bool
OUT
Bool
CLK
Bool
Q
Bool
S7-1200 Programmable controller
System Manual, 11/2011, A5E02486680-05
SCL
Description
Not available
LAD: The assigned bit "OUT" is TRUE when a positive transition (OFF-to-
ON) is detected on the power flow entering the coil. The power flow in
state always passes through the coil as the power flow out state. The P
coil can be located anywhere in the network.
FBD: The assigned bit "OUT" is TRUE when a positive transition (OFF-to-
ON) is detected on the logic state at the box input connection or on the
input bit assignment if the box is located at the start of a branch. The input
logic state always passes through the box as the output logic state. The
P= box can be located anywhere in the branch.
Not available
LAD: The assigned bit "OUT" is TRUE when a negative transition (ON-to-
OFF) is detected on the power flow entering the coil. The power flow in
state always passes through the coil as the power flow out state. The N
coil can be located anywhere in the network.
FBD: The assigned bit "OUT" is TRUE when a negative transition (ON-to-
OFF) is detected on the logic state at the box input connection or on the
input bit assignment if the box is located at the start of a branch. The input
logic state always passes through the box as the output logic state. The
N= box can be located anywhere in the branch.
Description
The Q output power flow or logic state is TRUE when a positive transition
(OFF-to-ON) is detected on the CLK input state (FBD) or CLK power flow
in (LAD).
In LAD, the P_TRIG instruction cannot be located at the beginning or end
of a network. In FBD, the P_TRIG instruction can be located anywhere
except the end of a branch.
The Q output power flow or logic state is TRUE when a negative transition
(ON-to-OFF) is detected on the CLK input state (FBD) or CLK power flow
in (LAD).
In LAD, the N_TRIG instruction cannot be located at the beginning or end
of a network. In FBD, the N_TRIG instruction can be located anywhere
except the end of a branch.
Description
Memory bit in which the previous state of the input is saved
Input bit whose transition edge is to be detected
Output bit which indicates a transition edge was detected
Power flow or input bit whose transition edge is to be detected
Output which indicates an edge was detected
100BBasic instructions
7.1 Bit logic
169