Timers, Counters And Code Blocks Supported By Cpu 1212C - Siemens S7-1200 System Manual
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Also See for S7-1200:
- Operating instructions manual (132 pages) ,
- Programming manualline (74 pages) ,
- Manual (46 pages)
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Technical specifications
A.3 CPU 1212C
Technical data
Pulse catch inputs
Time delay interrupts
Cyclic interrupts
Edge interrupts
Memory card
Real time clock accuracy
Real time clock retention time
The slower speed is applicable when the HSC is configured for quadrature mode of operation.
1
For CPU models with relay outputs, you must install a digital signal board (SB) to use the pulse outputs.
2
Table A- 30
Performance
Type of instruction
Boolean
Move Word
Real math
A.3.2
Timers, counters and code blocks supported by CPU 1212C
Table A- 31
Blocks, timers and counters supported by CPU 1212C
Element
Blocks
Type
Size
Quantity
Address range for FBs, FCs,
and DBs
Nesting depth
Monitoring
OBs
Program cycle
Startup
Time-delay interrupt
Cyclic interrupts
Hardware interrupts
Time error interrupts
Diagnostic error interrupts
Pull or plug of modules
Rack or station failure
Time of day
848
Description
8
4 total with 1 ms resolution
4 total with 1 ms resolution
8 rising and 8 falling (12 and 12 with optional signal board)
SIMATIC Memory Card (optional)
+/- 60 seconds/month
20 days typ./12 days min. at 40 °C (maintenance-free Super Capacitor)
Execution speed
0.08 μs/instruction
1.7 μs/instruction
2.3 μs/instruction
Description
OB, FB, FC, DB
50 Kbytes
Up to 1024 blocks total (OBs + FBs + FCs + DBs)
FB and FC: 1 to 65535 (such as FB 1 to FB 65535)
DB: 1 to 59999
16 from the program cycle or startup OB
6 from any interrupt event OB
Status of 2 code blocks can be monitored simultaneously
Multiple
Multiple
4 (1 per event)
4 (1 per event)
50 (1 per event)
1
1
1
1
Multiple
S7-1200 Programmable controller
System Manual, 03/2014, A5E02486680-AG
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