Cisco Asr 1000 Series Aggregation Services Routers Sip And Spa Software Configuration Guide, Cisco Ios - Cisco ASR 1000 Series Software Configuration Manual
Aggregation services routers sip and spa, cisco ios xe everest 16.5
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Also See for ASR 1000 Series:
- Configuration manual (442 pages) ,
- Replacing (120 pages) ,
- Common criteria operational user guidance and preparative procedures (72 pages)
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Configuration Examples
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CT3 1/0/0.2 is up.
Hardware is SPA-1XCHSTM1/OC3
IO FPGA version: 1.7, HDLC Framer version: 0
T3/T1 Framer(1) version: 1
Sonet/SDH Framer version: 0
SUBRATE FPGA version: 1.4
HDLC controller available FIFO buffers 3760
Applique type is Channelized T3 to T1
No alarms detected.
Framing is M23, Cablelength is 224
Clock Source is Internal
Equipment customer loopback
Data in current interval (356 seconds elapsed):
(Remaining output omitted)
Configuration Examples
This section includes the following configuration examples:
Example of T3 Framing Configuration
The following example configures framing on a T3 interface:
! Specify the interface to configure and enter interface configuration mode.
!
Router(config)# controller sonet 3/0/0
!
! Select the STS mode.
!
Router(config-controller)# sts-1 2
!
!Select the framing mode.
!
Router(config-controller)# t3 framing m23
Example of Cyclic Redundancy Check Configuration
The following example configures CRC on a T1 interface:
! Specify the interface to configure and enter interface configuration mode.
!
Router(config)# interface serial 2/0/0.1
!
! Specify the CRC type.
Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide, Cisco IOS
XE Everest 16.5
320
Configuring the 1-Port Channelized OC-3/STM-1 SPA and 1-Port Channelized OC-12/STM-4 SPA
0 Far-end code violations, 0 FERF Defect Secs
0 AIS Defect Secs, 0 LOS Defect Secs
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
0 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
0 Severely Errored Line Secs
0 Far-End Errored Secs, 0 Far-End Severely Errored Secs
0 CP-bit Far-end Unavailable Secs
0 Near-end path failures, 0 Far-end path failures
0 Far-end code violations, 0 FERF Defect Secs
0 AIS Defect Secs, 0 LOS Defect Secs
OL-14127-17
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